Imaging element and imaging device

Patent metadata

Field	Value
Publication number	US-2024030264-A1
Application number	US-202118255833-A
Country	US
Kind code	A1
Filing date	Dec 2, 2021
Priority date	Dec 10, 2020
Publication date	Jan 25, 2024
Grant date	—

Abstract

To downsize an imaging element formed by stacking a plurality of semiconductor substrates. The imaging element includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate includes a photoelectric conversion section that performs photoelectric conversion of incident light. The second semiconductor substrate includes a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion, an element isolating region that isolates elements of the pixel circuit, and a high impurity concentration region which is disposed below the element isolating region and having a high impurity concentration and is connected to the first semiconductor substrate in order to use a reference potential in common, with the first semiconductor substrate being stacked on a back surface side of the second semiconductor substrate.

First claim

1 . An imaging element comprising:
a first semiconductor substrate including a photoelectric conversion section that performs photoelectric conversion of incident light; and a second semiconductor substrate that includes a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion, an element isolating region that isolates elements of the pixel circuit, and a high impurity concentration region which is disposed below the element isolating region and having a high impurity concentration and is connected to the first semiconductor substrate in order to use a reference potential in common, with the first semiconductor substrate being stacked on a back surface side of the second semiconductor substrate.

2 . The imaging element according to claim 1 , further comprising a connecting location that connects the high impurity concentration region and the first semiconductor substrate to each other.

3 . The imaging element according to claim 2 ,
wherein the high impurity concentration region is disposed in a well region of the second semiconductor substrate, and the connecting location connects the high impurity concentration region and the well region of the first semiconductor substrate to each other.

4 . The imaging element according to claim 2 , wherein the connecting location is formed of silicon.

5 . The imaging element according to claim 2 , further comprising a second connecting location that is disposed on a front surface side of the second semiconductor substrate and supplies the reference potential.

6 . The imaging element according to claim 5 , wherein the second connecting location is disposed in the element isolating region and connected to the high impurity concentration region.

7 . The imaging element according to claim 5 , wherein the second connecting location is disposed adjacent to the element isolating region.

8 . The imaging element according to claim 5 , further comprising a third semiconductor substrate stacked on a front surface side of the second semiconductor substrate and connected to the second connecting location.

9 . The imaging element according to claim 5 , wherein the second connecting location is formed of metal.

10 . The imaging element according to claim 5 , wherein the second connecting location is formed of silicon.

11 . The imaging element according to claim 1 , wherein the high impurity concentration region has an impurity concentration of 5×10 17 cm −3 or more.

12 . The imaging element according to claim 1 ,
wherein the first semiconductor substrate includes: a charge holding section that holds a charge generated by the photoelectric conversion; and a charge transfer section that transfers the charge from the photoelectric conversion section to the charge holding section, and the pixel circuit generates an image signal according to the held charge.

13 . The imaging element according to claim 1 , further comprising a semiconductor region disposed in a layer same as a layer of the second semiconductor substrate.

14 . The imaging element according to claim 13 , wherein a reference potential different from the reference potential is supplied to the semiconductor region.

15 . The imaging element according to claim 14 ,
wherein the high impurity concentration region is disposed in a well region of the second semiconductor substrate, and the semiconductor region is configured in a well region having a conductivity type different from a conductivity type of a well region of the second semiconductor substrate.

16 . The imaging element according to claim 13 , wherein a transistor that amplifies a signal based on a charge generated by the photoelectric conversion in the pixel circuit is disposed in the semiconductor region.

17 . The imaging element according to claim 13 , wherein a transistor that controls output of the image signal in the pixel circuit is disposed in the semiconductor region.

18 . An imaging device comprising:
a first semiconductor substrate including a photoelectric conversion section that performs photoelectric conversion of incident light; a second semiconductor substrate that includes a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion, an element isolating region that isolates elements of the pixel circuit, and a high impurity concentration region which is disposed below the element isolating region and having a high impurity concentration and is connected to the first semiconductor substrate in order to use a reference potential in common, with the first semiconductor substrate being stacked on a back surface side of the second semiconductor substrate; and a processing circuit that processes the generated image signal.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Honjo Akiko
• Miyake Shinichi

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10F39/182 Primary

  Colour image sensors · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title