System, method and/or apparatus for magnetic memory testing

Patent metadata

Field	Value
Publication number	US-2024029811-A1
Application number	US-202217814418-A
Country	US
Kind code	A1
Filing date	Jul 22, 2022
Priority date	Jul 22, 2022
Publication date	Jan 25, 2024
Grant date	—

Abstract

Briefly, embodiments, such as methods and/or systems for operations and/or procedures to test magnetic memory devices. In a particular implementation, a bit error rate of a magnetic memory device may be estimated based, at least in part, on an observed bit error rate in the presence of an externally applied magnetic field.

First claim

What is claimed is:

1 . A method comprising:
providing an integrated magnetic memory device comprising a plurality of memory cells; writing to at least some of the plurality of memory cells according to a test pattern; reading states of the at least some of the plurality of memory cells; while the writing to the at least some of the plurality of memory cells according to the test pattern or the reading states of the at least some of the plurality of memory cells, applying a magnetic field from an external magnetic source to the integrated magnetic memory device; determining an observed bit error rate of the integrated magnetic memory device based, at least in part, on a comparison of the read states to the test pattern; and estimating an operational bit error rate of the integrated magnetic memory device in an absence of an externally applied magnetic field based, at least in part, on the observed bit error rate.

2 . The method of claim 1 , and further comprising:
varying the test pattern over read and write cycles; and varying application of the magnetic field from the external magnetic source to the integrated magnetic memory device in synchronous with variations in the test pattern over the read and write cycles.

3 . The method of claim 2 , wherein varying application of the magnetic field from the external magnetic source to the integrated magnetic memory device comprises:
varying a polarity of the magnetic field; and/or varying an intensity of the magnetic field.

4 . The method of claim 3 , wherein varying the intensity of the magnetic field comprises switching the magnetic field on and off in synchronous with read and write cycles.

5 . The method of claim 1 , and wherein estimating the operational bit error rate of the integrated magnetic memory device in the absence of the externally applied magnetic field further comprises:
determining an expected external magnetic field for a benchmark magnetic memory device to provide the observed bit error rate in the benchmark magnetic memory device; and estimating the operational bit error rate of the integrated magnetic memory device in the absence of the externally applied magnetic field based, at least in part, on expected bit error rate behavior of the benchmark magnetic memory device and a difference between the expected external magnetic field for a benchmark magnetic memory device to provide the observed bit error rate in the benchmark magnetic memory device and a magnitude of the magnetic field from the external magnetic source.

6 . The method of claim 1 , wherein estimating the operational bit error rate of the integrated magnetic memory device in the absence of the externally applied magnetic field further comprises extrapolating the estimated operational bit error rate from a plot of bit error rate of a benchmark magnetic memory device versus a magnitude of a magnetic field applied to the benchmark magnetic memory device.

7 . The method of claim 1 , wherein the memory cells comprise magnetic tunnel junctions (MTJs), the MTJs comprising a fixed magnetic layer having a fixed magnetic polarization, and wherein applying the magnetic field from the external magnetic source further comprises applying the magnetic field in a same magnetic direction as the fixed magnetic polarization.

8 . The method of claim 7 , wherein writing to at least some of the plurality of memory cells comprises changing states of selected ones of the memory cells from a P state to an AP state according to the test pattern, and wherein determining the observed bit error rate of the integrated magnetic memory device comprises observing a write error rate based, at least in part, on states read from the selected ones of the memory cells.

9 . The method of claim 1 , wherein:
the memory cells comprise magnetic tunnel junctions (MTJs), the MTJs comprising a fixed magnetic layer having a fixed magnetic polarization; and applying the magnetic field from the external magnetic source further comprises applying the magnetic field in a direction opposite the fixed magnetic polarization.

10 . The method of claim 9 , wherein writing to at least some of the plurality of memory cells comprises changing states of selected ones of the memory cells from an AP state to an P state according to the test pattern, and wherein determining the observed bit error rate of the integrated magnetic memory device observing a read error rate based, at least in part, on states read from the selected ones of the memory cells.

11 . A computing device comprising:
one or more processors to: obtain states read from at some of a plurality of memory cells of an integrated magnetic memory device in a read cycle, the at least some of the plurality of memory cells having been written to in a write cycle according to a test pattern, wherein a magnetic field having been applied from an external magnetic source to the integrated magnetic memory device during the write cycle or the read cycle; determine an observed bit error rate of the integrated magnetic memory device based, at least in part, on a comparison of the read states to the test pattern; and estimate an operational bit error rate of the integrated magnetic memory device in an absence of an externally applied magnetic field based, at least in part, on the observed bit error rate.

12 . The computing device of claim 11 , wherein the one or more processors are further to:
vary the test pattern over read and write cycles; and vary application of the magnetic field from the external magnetic source to the integrated magnetic memory device in synchronous with variations in the test pattern over the read and write cycles.

13 . The computing device of claim 12 , wherein the one or more processors are further to:
vary a polarity of the magnetic field; and/or varying an intensity of the magnetic field to thereby vary application of the magnetic field from the external magnetic source to the integrated magnetic memory device.

14 . The computing device of claim 13 , wherein the one or more processors are further to switch the magnetic field on and off in synchronous with read and write cycles to thereby vary the intensity of the magnetic field.

15 . The computing device of claim 11 , and wherein the one or more processors are further to estimate the operational bit error rate of the integrated magnetic memory device in the absence of the externally applied magnetic field based, at least in part, on expected bit error rate behavior of a benchmark magnetic memory device and a difference between an expected external magnetic field for a benchmark magnetic memory device to provide the observed bit error rate in the benchmark magnetic memory device and a magnitude of the magnetic field from the external magnetic source.

16 . The computing device of claim 11 , wherein the one or more processors are further to extrapolate the estimated operational bit error rate from a plot of bit error rate of a benchmark magnetic memory device versus a magnitude of a magnetic field applied to the benchmark magnetic memory device.

17 . The computing device of claim 11 , wherein the memory cells comprise magnetic tunnel junctions (MTJs), the MTJs comprising a fixed magnetic layer having a fixed magnetic polarization, and wherein application of the magnetic field from the external magnetic source further to comprise application of the magnetic field in a same magnetic direction as the fixed magnetic polarization.

18 . The computing device of claim 17 , wherein the one or more processors are furt

Assignees

• Advanced Risc Mach Ltd

Inventors

• Prabhat Pranay
• Bhargava Mudit
• Redondo Fernando Garcia

Classifications

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/50 Primary

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C2029/5002

  Characteristic · CPC title

• G11C29/50016

  of retention · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title