Apparatus with timing control of array events

Patent metadata

Field	Value
Publication number	US-2024029767-A1
Application number	US-202217868695-A
Country	US
Kind code	A1
Filing date	Jul 19, 2022
Priority date	Jul 19, 2022
Publication date	Jan 25, 2024
Grant date	—

Abstract

Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include a master die and a slave die communicatively coupled to each other through an internal bus. The apparatus can be configured to use an internal command and/or a data clock to coordinate the storage/write operation at the slave die instead of or in addition to a command address clock.

First claim

What is claimed is:

1 . An apparatus, comprising:
a master die configured to communicate with a device external to the apparatus; at least one slave die electrically coupled to the master die and configured to communicate with the master die using an inter-die bus; wherein the master die is configured to:
receive column address data on one or more command address pins aligned with a command address clock;
receive write data on one or more DQ pads aligned with a data clock;
create an internal write command aligned with the data clock;
send a first portion of the write data and the internal write command to a memory array of the master die;
send a second portion of the write data and the internal write command to the at least one slave die using the inter-die bus;
wherein the at least one slave die is configured to locally store the second portion using the internal write command to leverage the data clock in synchronizing the internal write command as a trigger for a local write operation and an availability of the corresponding second portion of the write data.

2 . The apparatus of claim 1 , wherein the master die is further configured to:
store the column address data in a master die First-In First-Out (FIFO) buffer; and release the column address data from the master die FIFO buffer based on the internal write command for temporally aligning the column address data with the data clock within the master die.

3 . The apparatus of claim 2 , wherein the master die is further configured to:
latch the write address data and the column address data at the memory array according to the internal write command instead of a command-address clock.

4 . The apparatus of claim 1 , wherein the at least one slave die is further configured to:
receive the second portion of the write data aligned with the data clock from the inter-die bus and one or more linked data pads of the master die.

5 . The apparatus of claim 1 , wherein the at least one slave die is further configured to:
store a portion of the column address data in a slave die FIFO buffer; and release the stored portion of the column address data from the slave die FIFO buffer based on the internal write command for temporally aligning the column address data with the data clock within the at least one slave die.

6 . The apparatus of claim 1 , wherein the at least one slave die is further configured to:
send a portion of the write data according to the internal write command internally from one or more linked data pads to a slave memory array of the at least one slave die, wherein the portion of the write data and the write command are both temporally aligned with the data clock.

7 . The apparatus of claim 1 , wherein the apparatus comprises a Dynamic Random-Access Memory (DRAM) device, wherein the master die and slave each include local memory arrays and local access circuits that are configured to contemporaneously store and/or access different portions of the write data.

8 . A semiconductor memory device, comprising:
at least one slave die electrically coupled to a master die and configured to communicate with the master die using an inter-die bus, wherein the at least one slave die includes:
a slave memory array configured to store data locally on the at least one slave die;
the master die configured to communicate with a device external to the semiconductor memory device, the master die including:
a master memory array configured to store data locally on the master die;
the master die configured to:
receive column address data on one or more command address pins aligned with a command address clock;
receive write data on one or more DQ pads aligned with a data clock;
create an internal write command aligned with the data clock;
send a first portion of the write data and the internal write command to a memory array of the master die;
send a second portion of the write data and the internal write command to the at least one slave die using the inter-die bus;

wherein the at least one slave die is configured to locally store the second portion using the internal write command to leverage the data clock in synchronizing the internal write command as a trigger for a local write operation and an availability of the corresponding second portion of the write data.

9 . The semiconductor memory device of claim 8 , wherein the master die is further configured to:
store the column address data in a master die First-In First-Out (FIFO) buffer; and release the column address data from the master die FIFO buffer based on the internal write command for temporally aligning the column address data with the data clock within the master die.

10 . The semiconductor memory device of claim 9 , wherein the master die is further configured to:
latch the write address data and the column address data at the memory array according to the internal write command instead of a command-address clock.

11 . The semiconductor memory device of claim 8 , wherein the at least one slave die is further configured to:
receive the second portion of the write data aligned with the data clock from the inter-die bus and one or more linked data pads of the master die.

12 . The semiconductor memory device of claim 8 , wherein the at least one slave die is further configured to:
store a portion of the column address data in a slave die FIFO buffer; and release the stored portion of the column address data from the slave die FIFO buffer based on the internal write command for temporally aligning the column address data with the data clock within the at least one slave die.

13 . The semiconductor memory device of claim 8 , wherein the at least one slave die is further configured to:
send a portion of the write data according to the internal write command internally from one or more linked data pads to a slave memory array of the at least one slave die, wherein the portion of the write data and the write command are both temporally aligned with the data clock.

14 . The semiconductor memory device of claim 8 , wherein the semiconductor memory device comprises a Dynamic Random-Access Memory (DRAM) device, wherein the master die and slave each include local memory arrays and local access circuits that are configured to contemporaneously store and/or access different portions of the write data.

15 . A method of operating an apparatus comprising a master die coupled to at least one slave die, the method comprising:
receiving column address data on one or more command address pins aligned with a command address clock; receiving write data on one or more DQ pads aligned with a data clock; creating an internal write command aligned with the data clock; sending a first portion of the write data and the internal write command to a memory array of the master die; and sending a second portion of the write data and the internal write command to the at least one slave die using an inter-die bus.

16 . The method of claim 15 , further comprising:
storing the column address data in a master die First-In First-Out (FIFO) buffer; and releasing the column address data from the master die FIFO buffer based on the internal write command for temporally aligning the column address data with the data clock within the master die.

17 . The method of claim 16 , further comprising:
latching the write address data and the column address data at the memory array according to the internal write command instead of a command-address clock.

18 . The method of claim 15 , further comprisin

Assignees

• Micron Technology Inc

Inventors

• Hadrick Mark K

Classifications

• G11C7/1093 Primary

  Input synchronization · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title