Chip capacitor including capacitor wires
US-12080479-B2 · Sep 3, 2024 · US
US2024021663A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2024021663-A1 |
| Application number | US-202318213473-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 23, 2023 |
| Priority date | Jul 13, 2022 |
| Publication date | Jan 18, 2024 |
| Grant date | — |
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A wire capacitor includes a wire structure extending in a longitudinal direction and a conductive layer covering an outer surface of the wire structure. The wire structure includes a core electrode line having a wire shape and extending in the longitudinal direction and a dielectric line surrounding an outer surface of the core electrode line and extending in the longitudinal direction. The wire structure has a first end and a second end which are opposite to each other in the longitudinal direction, and the conductive layer exposes an outer circumference of the first end and the second end of the wire structure.
Opening claim text (preview).
1 - 4 . (canceled) 5 . A wire capacitor comprising: a wire structure extending in a longitudinal direction; and a conductive layer covering an outer surface of the wire structure, wherein the wire structure includes: a core electrode line having a wire shape and extending in the longitudinal direction; and a dielectric line surrounding an outer surface of the core electrode line and extending in the longitudinal direction, wherein the wire structure has a first end and a second end which are opposite to each other in the longitudinal direction, and wherein the conductive layer exposes an outer circumference of the first end and the second end of the wire structure. 6 . The wire capacitor of claim 5 , wherein the conductive layer includes conductive paste. 7 . The wire capacitor of claim 5 , wherein the conductive layer covers an outer surface of the dielectric line and contacts the dielectric line. 8 . The wire capacitor of claim 5 , wherein the wire structure further includes a passivation line surrounding an outer surface of the dielectric line and extending in the longitudinal direction, and wherein the conductive layer covers an outer surface of the passivation line and contacts the passivation line. 9 . The wire capacitor of claim 5 , wherein the wire structure further includes an outer electrode line surrounding an outer surface of the dielectric line and extending in the longitudinal direction, wherein the outer electrode line exposes an outer circumference of the dielectric line, at the first end and the second end of the wire structure, and wherein the conductive layer covers an outer surface of the outer electrode line. 10 . The wire capacitor of claim 9 , wherein the conductive layer contacts the outer electrode line. 11 . The wire capacitor of claim 9 , wherein the wire structure further includes a passivation line surrounding an outer surface of the outer electrode line and extending in the longitudinal direction, wherein the passivation line exposes an outer circumference of the dielectric line, at the first end and the second end of the wire structure, and wherein the conductive layer is connected to the outer electrode line penetrating through the passivation line. 12 . The wire capacitor of claim 11 , wherein the conductive layer contacts the outer electrode line. 13 . The wire capacitor of claim 5 , wherein the wire structure further includes an adhesive layer interposed between the core electrode line and the dielectric line. 14 . The wire capacitor of claim 5 , wherein: the conductive layer is configured to be connected to a pad of a substrate associated with a semiconductor device, and the first end and the second end of the wire structure are each configured to be bonded to a pad of the substrate. 15 . An electronic device comprising: a substrate; and a wire capacitor electrically connected to the substrate, wherein the wire capacitor includes: a wire structure extending in a longitudinal direction; and a conductive layer covering an outer surface of the wire structure, wherein the wire structure includes: a core electrode line having a wire shape and extending in the longitudinal direction; and a dielectric line surrounding an outer surface of the core electrode line and extending in the longitudinal direction, wherein the wire structure includes a first end and a second end opposite to each other in the longitudinal direction, wherein the conductive layer exposes an outer circumference the first end and the second end of the wire structure, wherein the core electrode line is connected to the substrate by a wire bonding manner, at at least one of the first end and the second end of the wire structure, and wherein the conductive layer is electrically connected to the substrate. 16 . The electronic device of claim 15 , wherein the core electrode line is connected to the substrate by a ball bonding manner or a wedge bonding manner, at at least one of the first end and the second end of the wire structure. 17 . The electronic device of claim 15 , wherein the substrate includes pads on an upper surface of the substrate, and wherein ends of the core electrode line are connected a pair of first pads of the pads using a ball bonding manner or a wedge bonding manner, respectively, at the first end and the second end of the wire structure. 18 . The electronic device of claim 17 , wherein the conductive layer is connected to a second pad of the pads. 19 . The electronic device of claim 18 , wherein the conductive layer includes a conductive paste. 20 . The electronic device of claim 15 , wherein the wire structure further includes an outer electrode line surrounding an outer surface of the dielectric line and extending in the longitudinal direction, wherein the outer electrode line exposes an outer circumference of the dielectric line, at the first end and the second end of the wire structure, and wherein the conductive layer covers an outer surface of the outer electrode line, and the outer electrode line is electrically connected to the substrate through the conductive layer. 21 . The electronic device of claim 15 , wherein the substrate is a semiconductor chip, a redistribution substrate, a printed circuit board, or a lead frame. 22 . A wire capacitor for use in a semiconductor device or semiconductor module, the wire capacitor comprising: a wire structure extending in a longitudinal direction; and a conductive layer covering an outer surface of the wire structure, wherein the wire structure includes: a core electrode line having a wire shape and extending in the longitudinal direction; and a dielectric line surrounding an outer surface of the core electrode line and extending in the longitudinal direction, wherein the wire structure has a first end and a second end which are opposite to each other in the longitudinal direction, wherein the conductive layer exposes an outer circumference of the first end and the second end of the wire structure, wherein the conductive layer is configured to be connected to a pad of a substrate, and wherein the first end and the second end of the wire structure each are configured to be bonded to a pad of the substrate. 23 . The wire capacitor of claim 22 , wherein the conductive layer is configured to be connected to a pad of the substrate. 24 . The wire capacitor of claim 22 , wherein the dielectric line includes a material contacting the core electrode line and formed using physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
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