Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2024021498-A1
Application number	US-202118255385-A
Country	US
Kind code	A1
Filing date	Oct 14, 2021
Priority date	Dec 9, 2020
Publication date	Jan 18, 2024
Grant date	—

Abstract

A yield is improved in a semiconductor device in which a through electrode covered with an insulating film is formed. A semiconductor device includes a through electrode, an insulating film, and a wiring layer. In a semiconductor device including a through electrode, an insulating film, and a wiring layer, the through electrode penetrates the semiconductor substrate along a direction perpendicular to a predetermined front surface of the semiconductor substrate. Furthermore, the insulating film covers the through electrode. Moreover, the wiring layer includes a dummy gate disposed in a region between an outer periphery of the insulating film and an inner periphery of the insulating film on the front surface.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a through electrode that penetrates a semiconductor substrate along a direction perpendicular to a predetermined front surface of the semiconductor substrate; an insulating film covering the through electrode; and a wiring layer that includes a dummy gate disposed in a region between an outer periphery of the insulating film and an inner periphery of the insulating film on the front surface.

2 . The semiconductor device according to claim 1 , wherein
the dummy gate is not disposed inside the inner periphery.

3 . The semiconductor device according to claim 1 , wherein
the dummy gate is further disposed outside the outer periphery.

4 . The semiconductor device according to claim 3 , wherein
the semiconductor substrate includes an element isolation region formed under the wiring layer, and the dummy gate is disposed on an upper portion of the element isolation region.

5 . The semiconductor device according to claim 1 , wherein
an area ratio of the dummy gate is not less than ten percent.

6 . The semiconductor device according to claim 1 , wherein
a predetermined number of wirings are formed in the wiring layer, and a pitch of the wirings inside the outer periphery is substantially equal to a pitch of the wirings outside the outer periphery.

7 . The semiconductor device according to claim 1 , wherein
a gate electrode is further disposed in the wiring layer, and a material of the dummy gate is same as a material of the gate electrode.

8 . The semiconductor device according to claim 7 , wherein
the material of the dummy gate is any of polycrystalline silicon, amorphous silicon, tungsten, titanium, tantalum, and aluminum.

9 . The semiconductor device according to claim 1 , wherein
a gate electrode is further disposed in the wiring layer, and the material of the dummy gate is different from a material of the gate electrode.

10 . The semiconductor device according to claim 9 , wherein
a material of the dummy gate is silicon nitride.

11 . The semiconductor device according to claim 1 , wherein
in the through electrode, a cross-sectional area of an upper end on a front surface side is smaller than a cross-sectional area of a lower end on a back surface side with respect to the front surface, and the dummy gate is disposed between the outer periphery of the insulating film covering the upper end of the front surface and the inner periphery of the insulating film covering the upper end.

12 . The semiconductor device according to claim 1 , wherein
in the through electrode, a cross-sectional area of an upper end on a front surface side is larger than a cross-sectional area of a lower end on a back surface side with respect to the front surface, and the dummy gate is disposed between the outer periphery of the insulating film covering the lower end of the front surface and the inner periphery of the insulating film covering the lower end.

13 . The semiconductor device according to claim 1 , wherein
the semiconductor substrate includes an element isolation region formed over an entire surface of a region between the outer periphery of the insulating film and the inner periphery of the insulating film.

14 . The semiconductor device according to claim 1 , wherein
the semiconductor substrate includes an element isolation region formed in a part of a region between the outer periphery of the insulating film and the inner periphery of the insulating film, and the dummy gate is disposed on an upper side of the element isolation region.

15 . The semiconductor device according to claim 1 , wherein
a gate electrode of a Fin field-effect transistor (Fin-FET) is further disposed in the wiring layer.

16 . A method for manufacturing a semiconductor device comprising:
a first dummy gate formation procedure of forming a first dummy gate in a predetermined region between two concentric circles having different areas on a predetermined front surface of a semiconductor substrate; a polishing procedure of forming an interlayer insulating film on the front surface on which the first dummy gate is formed and polishing the interlayer insulating film; a second dummy gate formation procedure of removing the first dummy gate and forming a second dummy gate with a material different from a material of the first dummy gate in the predetermined region; and an insulating film formation procedure of forming, in the predetermined region, an insulating film for covering a through electrode penetrating the semiconductor substrate along a direction perpendicular to the front surface.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Shigetoshi Takushi
• Sasaki Naoto
• Saitou Kenichi

Classifications

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title