Multilayer ceramic electronic device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-2024021375-A1
Application number	US-202318351029-A
Country	US
Kind code	A1
Filing date	Jul 12, 2023
Priority date	Jul 14, 2022
Publication date	Jan 18, 2024
Grant date	—

Abstract

A multilayer ceramic electronic device includes a multilayer chip and external electrodes opposite to each other in a second direction orthogonal to a first direction in which internal electrode layers face and include a ceramic grain. 0.722×ln(W×T/E)−5.75+(αE−α0)+(t/12)≤6.02 is satisfied, when a dimension of the multilayer chip in the first direction is T (μm), a dimension of the multilayer chip in a third direction orthogonal to the first direction and the second direction is W (μm), a number of the internal electrode layers is E, a thermal expansion coefficient of the external electrodes is αE (×10−6/K), a thermal expansion coefficient of the multilayer chip is α0 (×10−6/K), and a maximum value of a thickness of the external electrodes on a main face in the first direction is t (μm).

First claim

What is claimed is:

1 . A multilayer ceramic electronic device comprising:
a multilayer chip having a plurality of dielectric layers and a plurality of internal electrode layers, the plurality of internal electrode layers facing each other with the plurality of dielectric layers respectively interposed therebetween; and a pair of external electrodes that are provided on two end faces of the multilayer chip opposite to each other in a second direction orthogonal to a first direction in which the plurality of internal electrode layers face each other, extend to a main face of the multilayer chip positioned at an end in the first direction, and include a ceramic grain, wherein 0.722×ln(W×T/E)−5.75+(α E −α 0 )+(t/12)≤6.02 is satisfied, when a dimension of the multilayer chip in the first direction is T (μm), a dimension of the multilayer chip in a third direction orthogonal to the first direction and the second direction is W (μm), a number of the plurality of internal electrode layers is E, a thermal expansion coefficient of the pair of external electrodes is α E (×10 −6 /K), a thermal expansion coefficient of the multilayer chip is α 0 (×10 −6 /K), and a maximum value of a thickness of the pair of external electrodes on the main face in the first direction is t (μm).

2 . The multilayer ceramic electronic device as claimed in claim 1 , wherein the ceramic grain is barium titanate or calcium zirconate.

3 . The multilayer ceramic electronic device as claimed in claim 1 , wherein E>10, when a dimension of the multilayer chip in the second direction is L, the L is 1000 μm, and the W is 500 μm.

4 . The multilayer ceramic electronic device as claimed in claim 1 , wherein E>50, when a dimension of the multilayer chip in the second direction is L, the L is 1600 μm, and the W is 800 μm.

5 . The multilayer ceramic electronic device as claimed in claim 1 , wherein E>15, when a dimension of the multilayer chip in the second direction is L, the L is 2100 μm, and the W is 2500 μm.

6 . The multilayer ceramic electronic device as claimed in claim 1 , wherein E>40, when a dimension of the multilayer chip in the second direction is L, the L is 3200 μm, and the W is 1600 μm.

7 . The multilayer ceramic electronic device as claimed in claim 1 , wherein E>100, when a dimension of the multilayer chip in the second direction is L, the L is 3200 μm, and the W is 2500 μm.

8 . The multilayer ceramic electronic device as claimed in claim 1 , wherein E>125, when a dimension of the multilayer chip in the second direction is L, the L is 4500 μm, and the W is 3200 μm.

9 . A manufacturing method of a multilayer ceramic electronic device comprising:
forming an internal electrode pattern on each of ceramic green sheets; forming a multilayer structure by stacking the ceramic green sheets on which the internal electrode pattern is formed; applying a conductive paste on two end faces of the multilayer structure opposite to each other; and by firing the multilayer structure and the conductive paste, forming a multilayer chip and a pair of external electrodes, the multilayer chip having a plurality of dielectric layers and a plurality of internal electrode layers, the plurality of internal electrode layers facing each other with the plurality of dielectric layers respectively interposed therebetween, wherein 0.722×ln(W×T/E)−5.75+(α E −α 0 )+(t/12)≤6.02 is satisfied, when a dimension of the multilayer chip in a first direction in which the plurality of internal electrode layers face each other is T (μm), a dimension of the multilayer chip in a third direction orthogonal to the first direction and a second direction in which the pair of external electrodes are opposite to each other is W (μm), a number of the plurality of internal electrode layers is E, a thermal expansion coefficient of the pair of external electrodes is α E (×10 −6 /K), a thermal expansion coefficient of the multilayer chip is α 0 (×10 −6 /K), and a maximum value of a thickness of the pair of external electrodes on a main face in the first direction is t (μm).

Assignees

• Taiyo Yuden Kk

Inventors

• Tahara Mikio
• Nakamura Tomoaki

Classifications

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title

• H01G4/1227

  based on alkaline earth titanates · CPC title

• C04B35/4682 Primary

  based on BaTiO3 perovskite phase · CPC title

• H01G4/008

  Selection of materials · CPC title