Storage module supporting prefetch function and operation method thereof

Patent metadata

Field	Value
Publication number	US-2024020235-A1
Application number	US-202318139112-A
Country	US
Kind code	A1
Filing date	Apr 25, 2023
Priority date	Jul 14, 2022
Publication date	Jan 18, 2024
Grant date	—

Abstract

A method of operating the storage module includes setting a characteristic value based on information on a prefetch size received from a host, and performing consecutive read operations in units of cache lines based on one prefetch read command received from the host.

First claim

What is claimed is:

1 . A method comprising:
setting a characteristic value based on information on a prefetch size received from a host; and performing consecutive read operations on a storage module in units of cache lines based on one prefetch read command received from the host.

2 . The method of claim 1 , wherein performing the consecutive read operations comprises:
consecutively performing the consecutive read operations with respect to different bank groups among a plurality of bank groups, based on an access time.

3 . The method of claim 2 , wherein consecutively performing the consecutive read operations with respect to the different bank groups comprises:
reading data corresponding to a size of a cache line with respect to a first bank group of the plurality of bank groups; and reading data corresponding to the size of the cache line with respect to a second bank group of the plurality of bank groups that is different from the first bank group, at an interval of the access time.

4 . The method of claim 3 , wherein a read operation with respect to the first bank group and the second bank group is sequentially performed in one direction based on a column stride scheme.

5 . The method of claim 2 , wherein consecutively performing the consecutive read operations with respect to the different bank groups comprises:
reading data of a first size with respect to a first bank group of the plurality of bank groups; and reading data of a second size less than the first size with respect to a second bank group of the plurality of bank groups that is different from the first bank group, at an interval of the access time, and wherein the first size is a same size as a size of a cache line.

6 . The method of claim 2 , wherein consecutively performing the consecutive read operations with respect to the different bank groups comprises:
reading data of a first size with respect to a first bank group of the plurality of bank groups; and reading data of a second size greater than the first size with respect to a second bank group of the plurality of bank groups that is different from the first bank group, at an interval of the access time, and wherein the second size is a same size as a size of a cache line.

7 . The method of claim 1 , wherein performing the consecutive read operations comprises:
consecutively performing the consecutive read operations with respect to banks of a same bank group based on an access time.

8 . The method of claim 1 , wherein the one prefetch read command is implemented with a ‘1’ bit.

9 . The method of claim 1 , wherein the characteristic value includes a characteristic value related to a number of the consecutive read operations to be consecutively performed.

10 . The method of claim 9 , wherein the characteristic value includes a characteristic value related to whether a read operation is to be performed on a same bank group of a plurality of bank groups, or whether a read operation is to be performed on different bank groups of the plurality of bank groups.

11 . The method of claim 1 , wherein the information on the prefetch size is transferred from the host through a mode register set (MRS) command or a mode register write (MRW) command, and
wherein, during an update delay time for setting the characteristic value, a non-setting command is not transmitted from the host.

12 . A storage module comprising:
a memory device including a volatile memory; and a memory controller configured to control the memory device, and wherein the memory controller includes:
a control module configured to decode a setting command received from a host to identify information on a prefetch size, and to determine a number of read operations to be performed consecutively based on the prefetch size; and
a register configured to store information on the number of read operations to be consecutively performed.

13 . The storage module of claim 12 , wherein the memory device includes a plurality of bank groups,
wherein the control module decodes the setting command to identify information on a toggle mode related to a bank group of the plurality of bank groups in which a read operation is to be performed, and wherein the register stores the information on the toggle mode.

14 . The storage module of claim 13 , wherein the control module outputs a control signal for performing the read operation on the memory device based on one prefetch read command received from the host, and
wherein the control signal is generated based on the information on the number of read operations to be consecutively performed and the information on the toggle mode.

15 . The storage module of claim 14 , wherein, when the toggle mode is enabled, the memory device alternately performs the read operations on different bank groups of the plurality of bank groups, based on the control signal.

16 . The storage module of claim 15 , wherein the read operations for each of the different bank groups are performed based on a column stride scheme.

17 . The storage module of claim 14 , wherein, when the toggle mode is disabled, the memory device consecutively performs the read operations on banks of a same bank group of the plurality of bank groups, based on the control signal.

18 . A memory system comprising:
a host configured to determine a number of cache lines to be prefetched into a cache memory; and a storage module including a volatile memory, and configured to receive the number of cache lines from the host and determine a number of read operations to be consecutively performed based on the number of cache lines, wherein the storage module consecutively performs a read operation in units of the cache lines based on one prefetch read command received from the host.

19 . The memory system of claim 18 , wherein the host includes:
a processor; a cache memory allocated to the processor; and a prefetch size decision module configured to determine the number of cache lines to be prefetched based on a workload to be performed by the processor.

20 . The memory system of claim 19 , wherein the host further includes:
a system address map manager configured to manage address information associated with data received from the storage module.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Wonjae
• Oh Doohwan
• Seo Ilwoong

Classifications

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F12/0844

  Multiple simultaneous or quasi-simultaneous cache accessing · CPC title

• G06F2212/6026

  Prefetching based on access pattern detection, e.g. stride based prefetch · CPC title

• G06F12/0607

  Interleaved addressing · CPC title

• G06F2212/1016

  Performance improvement · CPC title