Nonvolatile memory device, system including the same and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2024014157-A1
Application number	US-202318349017-A
Country	US
Kind code	A1
Filing date	Jul 7, 2023
Priority date	Sep 28, 2020
Publication date	Jan 11, 2024
Grant date	—

Abstract

A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

First claim

1 .- 20 . (canceled)

21 . A nonvolatile memory device comprising:
a substrate including a first surface and a second surface opposite to each other in a first direction; a ground selection line on the first surface of the substrate; a plurality of word lines stacked sequentially on the ground selection line; a channel structure penetrating the ground selection line and the plurality of word lines; a landing pad spaced apart from the ground selection line and the plurality of word lines in a second direction intersecting the first direction; a first input/output pad on the second surface of the substrate; a first front contact plug connected to a first surface of the landing pad and extending in the first direction; a first rear contact plug disposed between the landing pad and the first input/output pad and connected to a second surface of the landing pad that is opposite the first surface of the landing pad; and a landing pad cut contacting the land pad and extending in the first direction.

22 . The nonvolatile memory device of claim 21 , wherein the landing pad cut includes a first surface of the landing pad cut and a second surface of the landing pad cut,
wherein the second surface of the landing pad cut faces the substrate, and wherein a width of the first surface of the landing pad is greater than a width of the second surface of the landing pad.

23 . The nonvolatile memory device of claim 21 , wherein the first front contact plug and the first rear contact plug are disposed between the landing pad cut interposed therebetween.

24 . The nonvolatile memory device of claim 21 , wherein the channel structure includes a first sub channel structure, a second channel structure, and a channel contact surface between the first sub channel structure and the second channel structure.

25 . The nonvolatile memory device of claim 21 , further comprising a source region on the substrate,
wherein the channel structure includes a channel layer extending in the first direction, and wherein the source region is connected to a sidewall of the channel layer.

26 . The nonvolatile memory device of claim 21 , further comprising:
a second input/output pad on the second surface of the substrate, a second front contact plug connected to the first surface of the landing pad and extending in the first direction, and a second rear contact plug disposed between the landing pad and the second input/output pad.

27 . The nonvolatile memory device of claim 26 , wherein the first front contact plug is spaced apart from the land pad cut by a first distance on the first surface of the landing pad,
wherein the second front contact plug is spaced apart from the land pad cut by a second distance on the first surface of the landing pad, wherein the first rear contact plug is spaced apart from the land pad cut by a third distance on the second surface of the landing pad, wherein the second rear contact plug is spaced apart from the land pad cut by a fourth distance on the second surface of the landing pad, and wherein a sign of a first value obtained by subtracting the third distance from the first distance is the same as a sign of a second value obtained by subtracting the fourth distance from the second distance.

28 . The nonvolatile memory device of claim 21 , wherein the landing pad cut is in contact with the substrate.

29 . The nonvolatile memory device of claim 21 , wherein the landing pad cut is spatially spaced from the first surface of the substrate.

30 . The nonvolatile memory device of claim 21 , wherein the landing pad is disposed at a same height as the ground selection line.

31 . The nonvolatile memory device of claim 21 , wherein the landing pad is disposed at a same height as at least one of the plurality of word lines.

32 . The nonvolatile memory device of claim 21 , further comprising an upper bonding pad electrically connected to the first front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

33 . The nonvolatile memory device of claim 21 , wherein the substrate includes a semiconductor region formed of a semiconductor material,
wherein the semiconductor region has a first surface of the semiconductor region and a second surface of the semiconductor region opposite to each other in the first direction, wherein the first surface of the semiconductor region is planar shape, and wherein the second surface of the semiconductor region in uneven shape.

34 . A nonvolatile memory device comprising:
a peripheral region including a plurality of circuit elements; and a cell region which is electrically connected to the plurality of circuit elements and that stores data, wherein the cell region comprises: a substrate including a first surface and a second surface opposite to each other in a first direction; a ground selection line on the first surface of the substrate; a plurality of word lines stacked sequentially on the ground selection line; a channel structure penetrating the ground selection line and the plurality of word lines; a landing pad spaced apart from the ground selection line and the plurality of word lines in a second direction intersecting the first direction; a input/output pad on the second surface of the substrate; a front contact plug connected to a first surface of the landing pad and extending in the first direction; a rear contact plug disposed between the landing pad and the input/output pad and connected to a second surface of the landing pad that is opposite the first surface of the landing pad; a landing pad cut penetrating the land pad and extending in the first direction; and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of the plurality of circuit elements.

35 . The nonvolatile memory device of claim 34 , wherein the landing pad cut includes a first surface of the landing pad cut and a second surface of the landing pad cut,
wherein the second surface of the landing pad cut faces the substrate, and wherein a width of the first surface of the landing pad is greater than a width of the second surface of the landing pad.

36 . The nonvolatile memory device of claim 34 , wherein the channel structure includes a first sub channel structure, a second channel structure, and a channel contact surface between the first sub channel structure and the second channel structure.

37 . The nonvolatile memory device of claim 34 , wherein the landing pad cut is in contact with the substrate.

38 . The nonvolatile memory device of claim 34 , wherein the cell region further comprises a source region on the substrate,
wherein the channel structure includes a channel layer extending in the first direction, and wherein the source region is connected to the channel layer.

39 . The nonvolatile memory device of claim 34 , wherein the front contact plug and the rear contact plug are disposed between the landing pad cut interposed therebetween.

40 . A nonvolatile memory system comprising:
a main board; a nonvolatile memory device on the main board; and a controller electrically connected to the nonvolatile memory device on the main board, wherein the nonvolatile memory device comprises:
a substrate including a first surface and a second surface opposite to each other in a first direction;
a ground selection line on the first surface of the substrate;
a plurality of word lines stacked sequentially on the ground

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Jae Ho
• Kim Ji Won
• Hwang Sung-Min
• Lim Joon-Sung
• Sung Suk Kang

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title