Wafer storage and transport system and method of operation of wafer storage and transport system

US2024006215A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2024006215-A1
Application numberUS-202318195757-A
CountryUS
Kind codeA1
Filing dateMay 10, 2023
Priority dateJul 1, 2022
Publication dateJan 4, 2024
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A wafer storage and transport system includes a ceiling surface which includes a first surface and a second surface, a first traveling rail installed on the second surface, a second traveling rail which is spaced apart from the first surface in a third direction, and extends in a first direction, a transport unit which is movable in the first direction along the second traveling rail and transports a FOUP, storage spaces installed on the first surface and which may store the FOUP, an interface port installed on the second surface and which temporarily stores the FOUP, and an OHT which is movable along the first traveling rail, wherein the transport unit grasps the FOUP arranged in the storage spaces and transports the FOUP to the interface port, and the OHT grasps the FOUP temporarily stored in the interface port and transports the FOUP to a semiconductor facility.

First claim

Opening claim text (preview).

What is claimed is: 1 . A wafer storage and transport system comprising: a ceiling surface comprising a first surface and a second surface opposite to the first surface; a first traveling rail installed on the second surface; a second traveling rail spaced apart from the first surface in a third direction, and extending in a first direction; a transport unit which is movable in the first direction along the second traveling rail, and configured to transport a Front Opening Unified Pod (FOUP); storage spaces installed on the first surface and configured to store the FOUP such that the FOUP is arranged inside the storage spaces in the first direction and a second direction, and the FOUP is not arranged in the third direction; an interface port installed on the second surface and configured to temporarily store the FOUP; and an Overhead Hoist Transport (OHT) which is movable along the first traveling rail, wherein the transport unit is further configured to grasp the FOUP arranged in the storage spaces and transport the FOUP to the interface port, and wherein the OHT is configured to grasp the FOUP temporarily stored in the interface port and transport the FOUP to a semiconductor facility. 2 . The wafer storage and transport system of claim 1 , wherein the FOUP is arranged inside the interface port in the first direction and is not arranged in the second direction and the third direction. 3 . The wafer storage and transport system of claim 1 , wherein the interface port is installed between the storage spaces. 4 . The wafer storage and transport system of claim 1 , wherein the transport unit comprises: a pair of horizontal arms which are extendable in the second direction; a hand configured to grasp the FOUP; a plate which is connected to the pair of horizontal arms and fixes the hand; and a sub-arm which is connected to the plate and a main body of the transport unit, is extendable in the second direction, and has elasticity. 5 . The wafer storage and transport system of claim 4 , wherein the pair of horizontal arms comprises a first arm and a second arm, and wherein a distance between the first arm and the second arm in the first direction narrows, as the first arm and the second arm extend away from the main body of the transport unit in the second direction. 6 . The wafer storage and transport system of claim 4 , wherein the transport unit further comprises a vertical arm which is extendable in the third direction and configured to move the plate in the third direction, and wherein a diameter of the vertical arm narrows, as the vertical arm extends away from the main body of the transport unit in the third direction. 7 . The wafer storage and transport system of claim 1 , wherein the transport unit does not overlap the storage spaces in the third direction. 8 . The wafer storage and transport system of claim 1 , wherein a number of FOUPs arranged inside the storage spaces in the second direction is three to six. 9 . The wafer storage and transport system of claim 1 , wherein the storage spaces and the semiconductor facility do not overlap in the third direction. 10 . The wafer storage and transport system of claim 1 , wherein the first traveling rail and the second traveling rail are not connected to each other. 11 . The wafer storage and transport system of claim 1 , wherein the OHT is configured to travel between the interface port and the semiconductor facility under control of a controller. 12 . The wafer storage and transport system of claim 1 , wherein the transport unit is configured to travel between the interface port and the storage spaces under control of a controller. 13 . The wafer storage and transport system of claim 1 , further comprising: a piping connected to the storage spaces, wherein the piping is configured to supply nitrogen (N 2 ) to the FOUP. 14 . A wafer storage and transport system comprising: a first ceiling surface which comprises a first surface, a second surface opposite to the first surface, and an opening; a second ceiling surface which is spaced apart from the first ceiling surface in a third direction; a transport unit which is provided below the second ceiling surface and is movable in a first direction, the transport unit being configured to transport a Front Opening Unified Pod (FOUP), and the transport unit comprises: a pair of horizontal arms extendable in a second direction; and a vertical arm extendable in the third direction; a storage space which is installed on the first surface and configured to store the FOUP such that the FOUP is arranged inside the storage space in the first direction and the second direction, and the FOUP is not arranged in the third direction; an interface port installed on the second surface in a region that overlaps the opening in the third direction, and configured to temporarily store the FOUP such that the FOUP is arranged in a line inside the interface port in the first direction; and an Overhead Hoist Transport (OHT) which is movable along a first traveling rail installed on the second surface, wherein the transport unit is installed in a region that overlaps the interface port in the third direction, wherein the transport unit is further configured to extend the pair of horizontal arms in the second direction, extend the vertical arm in the third direction to grasp the FOUP arranged in the storage space, and transport the grasped FOUP by extending the vertical arm in the third direction to the interface port, wherein the pair of horizontal arms comprises a first arm and a second arm, and a distance between the first arm and the second arm in the first direction narrows, as the first arm and the second arm extend away from a main body of the transport unit in the second direction, wherein a diameter of the vertical arm narrows, as the vertical arm extends away from the main body of the transport unit in the third direction, and wherein the OHT is configured to transport the FOUP temporarily stored in the interface port to a semiconductor facility. 15 . The wafer storage and transport system of claim 14 , wherein the transport unit further comprises: a hand which is configured to grasp the FOUP; a plate which is connected to the pair of horizontal arms and which fixes the hand; and a sub-arm which is connected to the plate and the main body of the transport unit, and has elasticity. 16 . The wafer storage and transport system of claim 14 , further comprising: a piping connected to the storage space, wherein the piping is configured to supply nitrogen (N 2 ) to the FOUP. 17 . The wafer storage and transport system of claim 14 , further comprising: a second traveling rail which is installed below the second ceiling surface, is not connected to the first traveling rail, and extends in the first direction, wherein the transport unit is further configured to travel along the second traveling rail. 18 . The wafer storage and transport system of claim 14 , wherein the OHT is further configured to travel between the interface port and the semiconductor facility under control of a controller, and wherein the transport unit is further configured to travel between the interface port and the storage space under control of the controller. 19 . A method of operating a wafer storage and transport system, the method comprising: moving a transport unit along a second traveling rail in a first direction under control of a controller, wherein the transport unit comprises a pair of horizo

Assignees

Inventors

Classifications

  • Storage means · CPC title

  • Loading to or unloading from a conveyor · CPC title

  • Conveying cassettes, containers or carriers · CPC title

  • Mechanical details, e.g. rollers or belts · CPC title

  • Overhead conveying · CPC title

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What does patent US2024006215A1 cover?
A wafer storage and transport system includes a ceiling surface which includes a first surface and a second surface, a first traveling rail installed on the second surface, a second traveling rail which is spaced apart from the first surface in a third direction, and extends in a first direction, a transport unit which is movable in the first direction along the second traveling rail and transp…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P72/3202. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 04 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).