Display device

Patent metadata

Field	Value
Publication number	US-2023419882-A1
Application number	US-202318142237-A
Country	US
Kind code	A1
Filing date	May 2, 2023
Priority date	May 26, 2022
Publication date	Dec 28, 2023
Grant date	—

Abstract

A display device includes a display panel including a pixel including a pixel circuit and a light emitting element, a plurality of scan lines connected to the pixel circuit, an emission control line connected to the pixel circuit, and a data line connected to the pixel circuit. The pixel circuit includes a first capacitor connected to a first node and a second node opposite to the first node, a first circuit portion that includes a first transistor connected between the data line and the first node and a second transistor connected between the first transistor and the first node, and a second circuit portion connected to the second node and the light emitting element. Before the light emitting element emits light, a reference voltage is provided to a third node between the first transistor and the second transistor.

First claim

What is claimed is:

1 . A display device, comprising
a display panel including a plurality of pixels, each including a pixel circuit and a light emitting element, a plurality of scan lines connected to the pixel circuit, an emission control line connected to the pixel circuit, and a data line connected to the pixel circuit, wherein the pixel circuit includes:
a first capacitor connected to a first node and a second node opposite to the first node;
a first circuit portion including a first transistor and a second transistor, the first transistor being connected between the data line and the first node, and the second transistor being connected between the first transistor and the first node; and
a second circuit portion connected to the second node and the light emitting element,
wherein, before the light emitting element emits light, a reference voltage is provided to a third node between the first transistor and the second transistor.

2 . The display device of claim 1 , wherein
the first transistor is a p-type thin film transistor, and the second transistor is an n-type thin film transistor.

3 . The display device of claim 1 , wherein the first circuit portion further includes:
a third transistor connected between the third node and a reference voltage line to which the reference voltage is provided; and a second capacitor connected between the first node and a first drive voltage line to which a first drive voltage is applied.

4 . The display device of claim 3 , wherein the second circuit portion includes:
a fourth transistor connected between the second node and a first initialization voltage line to which a first initialization voltage is applied; a fifth transistor connected between the fourth transistor and the first initialization voltage line; a sixth transistor including a gate electrode connected to the second node, a first electrode connected to the first drive voltage line, and a second electrode; a seventh transistor connected between the second electrode of the sixth transistor and a node between the fourth transistor and the fifth transistor; an eighth transistor connected between the light emitting element and the second electrode of the sixth transistor; and a ninth transistor connected between a node between the light emitting element and the eighth transistor and a second initialization voltage line to which a second initialization voltage is applied, wherein the light emitting element is connected between the eighth transistor and a second drive voltage line to which a second drive voltage is applied.

5 . The display device of claim 4 , wherein
each of the third, fifth, sixth, seventh, eighth, and ninth transistors is a p-type thin film transistor, and the fourth transistor is an n-type thin film transistor.

6 . The display device of claim 4 , wherein the second transistor and the fourth transistor are controlled by a same scan signal.

7 . The display device of claim 4 , wherein, before the eighth transistor is turned on, the reference voltage is provided to the third node between the first transistor and the second transistor.

8 . The display device of claim 4 , wherein
the display panel is configured to operate in a single frequency mode or a multi-frequency mode, and in the multi-frequency mode, a first portion of the display panel operates at a first frequency, and a second portion of the display panel operates at a second frequency less than the first frequency.

9 . The display device of claim 8 , wherein the plurality of pixels includes:
a first pixel disposed in the first portion of the display panel; and a second pixel disposed in the second portion of the display panel, wherein the second and fourth transistors of the second pixel disposed in the second portion are turned off in the multi-frequency mode.

10 . The display device of claim 9 , wherein the first transistor of the second pixel disposed in the second portion is turned off in the multi-frequency mode.

11 . The display device of claim 4 , wherein the second circuit portion further includes:
a tenth transistor connected between the first drive voltage line and the first electrode of the sixth transistor; and an eleventh transistor connected between a node between the sixth transistor and the tenth transistor and a vias voltage line to which a bias voltage is provided.

12 . The display device of claim 11 , wherein each of the tenth and eleventh transistors is a p-type thin film transistor.

13 . A display device, comprising
a display panel including a first pixel and a second pixel spaced apart from the first pixel, and which is configured to operate in a single frequency mode or a multi-frequency mode, wherein each of the first pixel and the second pixel includes a pixel circuit and a light emitting element, wherein the pixel circuit includes:
a first capacitor connected to a first node and a second node opposite to the first node;
a first circuit portion including a first transistor and a second transistor, the first transistor being connected between a data line and the first node, and the second transistor being connected between the first transistor and the first node; and
a second circuit portion connected to the second node and the light emitting element,
wherein, in each of the single frequency mode and the multi-frequency mode, before the light emitting element emits light, a reference voltage is provided to a third node between the first transistor and the second transistor.

14 . The display device of claim 13 , wherein the first circuit portion further includes:
a third transistor connected between the third node and a reference voltage line to which the reference voltage is provided; and a second capacitor connected between the first node and a first drive voltage line to which a first drive voltage is applied.

15 . The display device of claim 14 , wherein the second circuit portion includes:
a fourth transistor connected between the second node and a first initialization voltage line to which a first initialization voltage is applied; a fifth transistor connected between the fourth transistor and the first initialization voltage line; a sixth transistor including a gate electrode connected to the second node, a first electrode connected to the first drive voltage line, and a second electrode; a seventh transistor connected between the second electrode of the sixth transistor and a node between the fourth transistor and the fifth transistor; an eighth transistor connected between the light emitting element and the second electrode of the sixth transistor; and a ninth transistor connected between a node between the light emitting element and the eighth transistor and a second initialization voltage line to which a second initialization voltage is applied.

16 . The display device of claim 15 , wherein, before the eighth transistor is turned on, the reference voltage is provided to the third node between the first transistor and the second transistor.

17 . The display device of claim 15 , wherein, in the multi-frequency mode, a first portion of the display panel operates at a first frequency, and a second portion of the display panel operates at a second frequency less than the first frequency,
wherein the first pixel is disposed in the first portion, and wherein the second pixel is disposed in the second portion.

18 . The display device of claim 17 , wherein the second and fourth transistors of the second pixel disposed in the second portion are turned off i

Assignees

• Samsung Display Co Ltd

Inventors

• Lim Jaekeun
• Gu Bon-Seog
• Kwon Sangan
• Kim Soon-Dong
• Roh Jinyoung
• Seo Hae-Kwan

Classifications

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title