Active matrix substrate and display device

Patent metadata

Field	Value
Publication number	US-2023418123-A1
Application number	US-202318211805-A
Country	US
Kind code	A1
Filing date	Jun 20, 2023
Priority date	Jun 22, 2022
Publication date	Dec 28, 2023
Grant date	—

Abstract

An active matrix substrate includes a pixel TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode disposed so as to face the oxide semiconductor layer with the gate insulating layer interposed therebetween, a plurality of gate lines, an interlayer insulating layer provided so as to cover the gate electrode and the plurality of gate lines, a plurality of source lines provided on the interlayer insulating layer, an upper insulating layer provided so as to cover the plurality of source lines, and an organic insulating layer provided on the upper insulating layer. The interlayer insulating layer includes a first layer formed of silicon oxide, a second layer provided on the first layer and formed of silicon nitride, and a third layer provided on the second layer and formed of silicon oxide.

First claim

1 . An active matrix substrate comprising:
a plurality of pixel regions arranged in a matrix; a substrate; a pixel TFT supported by the substrate and provided corresponding to each of the plurality of pixel regions, the pixel TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode facing the oxide semiconductor layer with the gate insulating layer interposed therebetween; a plurality of gate lines extending in a row direction and formed of the same conductive film as the gate electrode; an interlayer insulating layer covering the gate electrode and the plurality of gate lines; a plurality of source lines extending in a column direction and provided on the interlayer insulating layer; an upper insulating layer covering the plurality of source lines; and an organic insulating layer provided on the upper insulating layer, wherein the interlayer insulating layer includes a first layer formed of silicon oxide, a second layer provided on the first layer and formed of silicon nitride, and a third layer provided on the second layer and formed of silicon oxide.

2 . The active matrix substrate according to claim 1 ,
wherein a thickness of the third layer of the interlayer insulating layer is 50 nm or more.

3 . The active matrix substrate according to claim 1 ,
wherein the upper insulating layer includes a fourth layer formed of silicon oxide, and a fifth layer provided on the fourth layer and formed of silicon nitride.

4 . The active matrix substrate according to claim 1 ,
wherein the upper insulating layer includes a fourth layer formed of silicon nitride, a fifth layer provided on the fourth layer and formed of silicon oxide, and a sixth layer provided on the fifth layer and formed of silicon nitride.

5 . The active matrix substrate according to claim 1 ,
wherein the upper insulating layer includes only a fourth layer formed of silicon nitride.

6 . The active matrix substrate according to claim 1 , further comprising:
a gate metal layer including the gate electrode and the plurality of gate lines; and a source metal layer including the plurality of source lines, wherein when a region in which the gate metal layer and the source metal layer overlap each other with the interlayer insulating layer interposed therebetween is referred to as an intersection region, the organic insulating layer and the upper insulating layer include an opening formed over both the organic insulating layer and the upper insulating layer and overlapping the intersection region.

7 . The active matrix substrate according to claim 6 ,
wherein the interlayer insulating layer includes a portion including the first layer and the second layer and not including the third layer in a region overlapping the opening.

8 . The active matrix substrate according to claim 7 ,
wherein a thickness of the second layer included in the portion of the interlayer insulating layer is 50 nm or more.

9 . The active matrix substrate according to claim 6 ,
wherein the interlayer insulating layer includes the first layer, the second layer, and the third layer in the entirety of the region overlapping the opening.

10 . The active matrix substrate according to claim 6 , further comprising:
a gate line drive circuit configured to drive the plurality of gate lines, the gate line drive circuit being monolithically formed on the substrate, wherein the opening included in the organic insulating layer and the upper insulating layer is located in the gate line drive circuit.

11 . The active matrix substrate according to claim 1 ,
wherein the oxide semiconductor layer includes an In—Ga—Zn—O based semiconductor.

12 . The active matrix substrate according to claim 11 ,
wherein the In—Ga—Zn—O based semiconductor includes a crystalline portion.

13 . A display device comprising:
the active matrix substrate according to claim 1 .

14 . The display device according to claim 13 ,
wherein the display device is a liquid crystal display device including a counter substrate facing the active matrix substrate, and a liquid crystal layer provided between the active matrix substrate and the counter substrate.

Assignees

• Sharp Display Technology Corp

Inventors

• Takahata Hitoshi
• Daitoh Tohru
• Kikuchi Tetsuo
• Suzuki Masahiko
• Nishimiya Setsuji

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title