Using stateful traffic management data to perform packet processing

Patent metadata

Field	Value
Publication number	US-2023412520-A1
Application number	US-202318214665-A
Country	US
Kind code	A1
Filing date	Jun 27, 2023
Priority date	Jul 23, 2017
Publication date	Dec 21, 2023
Grant date	—

Abstract

Some embodiments provide a method for an ingress packet processing pipeline of a network forwarding integrated circuit (IC). The ingress packet processing pipeline is for receiving packets from a port of the network forwarding IC and processing the packets to assign different packets to different queues of a traffic management unit of the network forwarding IC. The method receives state data from the traffic management unit. The method stores the state data in a stateful table. The method assigns a particular packet to a particular queue based on the state data received from the traffic management unit and stored in the stateful table.

First claim

1 . (canceled)

2 . An integrated circuit to be associated with a network, the integrated circuit to be used in network forwarding operations associated with at least one network destination, the integrated circuit comprising:
configurable ingress pipelines to process packet data received by the integrated circuit; traffic manager circuitry to (1) queue the packet data processed by the configurable ingress pipelines, and (2) dequeue the packet data queued by the traffic manager circuitry; and configurable egress pipelines to process, for use in forwarding to the at least one network destination, the packet data dequeued by the traffic manager circuitry; wherein:
the configurable ingress pipelines and/or the configurable egress pipelines are configurable to comprise at least one parser, at least one match-action stage, and at least one other stage;
the at least one parser is to identify received packet header field data for use by the at least one match-action stage and the at least one other stage;
the at least one match-action stage is to perform packet data processing associated with the network forwarding operations;
the at least one other stage is to generate other packet data for use the forwarding to the at least one network destination;
the packet data processing is configurable, at least in part, based upon control plane-generated configuration data to be received by the integrated circuit from a local control plane or a remote control plane;
the packet data processing is to be based, at least in part, upon match table data that is configurable to comprise TCAM match table data and/or exact match table data;
the match table data comprises match entry data to be matched against the packet header field data to determine at least one corresponding action to be performed;
the integrated circuit is to generate queue state data:
in response, at least in part, to packet data queuing/dequeuing by the traffic management circuitry; and
based upon queue occupancy information and queue identification data of the packet data queued by the traffic manager circuitry;

the queue state data is to be used in association with at least one mapping that is based upon memory location data and the queue identification data;
at least one pipeline comprised in the ingress pipelines and egress pipelines is configurable to perform at least one congestion-related packet data processing decision based upon the queue state data; and
the at least one congestion-related packet data processing decision is configurable to comprise at least one packet data queue/drop decision.

3 . The integrated circuit of claim 2 , wherein:
the ingress pipelines are configurable to use the queue state data in association with at least one flow-related statistical determination.

4 . The integrated circuit of claim 3 , wherein:
the queue occupancy information indicates one or more of the following:
queue depth information; and/or
buffer usage information.

5 . The integrated circuit of claim 4 , wherein:
the at least one congestion-related packet data processing decision is configurable to comprise one or more of the following:
at least one queue re-assignment decision; and/or
at least one threshold-based queue/drop decision.

6 . The integrated circuit of claim 5 , wherein:
the traffic manager circuitry comprises:
queues for use in the packet data queuing; and
the integrated circuit also comprises:
switch fabric and replication circuitry for use in:
directing the packet data to the queues; and
replicating at least one portion of the packet data for use in packet data broadcast or multicast.

7 . At least one non-transitory memory storing instructions for being executed by an integrated circuit, the integrated circuit to be associated with a network, the integrated circuit to be used in network forwarding operations associated with at least one network destination, the integrated circuit comprising configurable ingress pipelines, traffic manager circuitry, and configurable egress pipelines, the instructions, when executed by the integrated circuit, resulting in the integrated circuit being configured to perform processing operations comprising:
processing, by the configurable ingress pipelines, packet data received by the integrated circuit; queuing, by the traffic manager circuitry, the packet data processed by the configurable ingress pipelines; dequeuing, by the traffic manager circuitry, the packet data queued by the traffic manager circuitry; and processing, by the configurable egress pipelines, for use in forwarding to the at least one network destination, the packet data dequeued by the traffic manager circuitry; wherein:
the configurable ingress pipelines and/or the configurable egress pipelines are configurable to comprise at least one parser, at least one match-action stage, and at least one other stage;
the at least one parser is to identify received packet header field data for use by the at least one match-action stage and the at least one other stage;
the at least one match-action stage is to perform packet data processing associated with the network forwarding operations;
the at least one other stage is to generate other packet data for use the forwarding to the at least one network destination;
the packet data processing is configurable, at least in part, based upon control plane-generated configuration data to be received by the integrated circuit from a local control plane or a remote control plane;
the packet data processing is to be based, at least in part, upon match table data that is configurable to comprise TCAM match table data and/or exact match table data;
the match table data comprises match entry data to be matched against the packet header field data to determine at least one corresponding action to be performed;
the integrated circuit is to generate queue state data:
in response, at least in part, to packet data queuing/dequeuing by the traffic management circuitry; and
based upon queue occupancy information and queue identification data of the packet data queued by the traffic manager circuitry;

the queue state data is to be used in association with at least one mapping that is based upon memory location data and the queue identification data;
at least one pipeline comprised in the ingress pipelines and egress pipelines is configurable to perform at least one congestion-related packet data processing decision based upon the queue state data; and
the at least one congestion-related packet data processing decision is configurable to comprise at least one packet data queue/drop decision.

8 . The at least one non-transitory memory of claim 7 , wherein:
the ingress pipelines are configurable to use the queue state data in association with at least one flow-related statistical determination.

9 . The at least one non-transitory memory of claim 8 , wherein:
the queue occupancy information indicates one or more of the following:
queue depth information; and/or
buffer usage information.

10 . The at least one non-transitory memory of claim 9 , wherein:
the at least one congestion-related packet data processing decision is configurable to comprise one or more of the following:
at least one queue re-assignment decision; and/or
at least one threshold-based queue/drop decision.

11 . The at least one non-transitory memory of claim 10 , wherein:
the traffic manager circuitry comprises:
queues for use in the packet data queuing; and
the integrated circuit also comprises:
switch fabric and replication circuitry for use in:
directing the packet data to the queues; and
replicating at least one portion of the packet data for u

Assignees

• Barefoot Networks Inc

Inventors

• Li Yi
• Feng Michael
• Agrawal Anurag
• Lee Jeongkeun
• Kim Changhoon
• Chang Remy

Classifications

• H04L45/745

  Address table lookup; Address filtering · CPC title

• H04L47/6255 Primary

  queue load conditions, e.g. longest queue first · CPC title

• H04L49/3063 Primary

  Pipelined operation · CPC title

• H04L49/101

  using crossbar or matrix · CPC title

• H04L41/142

  using statistical or mathematical methods · CPC title