Logic circuit and semiconductor device

Patent metadata

Field	Value
Publication number	US-2023411410-A1
Application number	US-202318239928-A
Country	US
Kind code	A1
Filing date	Aug 30, 2023
Priority date	Oct 16, 2009
Publication date	Dec 21, 2023
Grant date	—

Abstract

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10 −13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

First claim

1 . A semiconductor device comprising:
a pixel portion having a first transistor and a light-emitting element electrically connected to the first transistor; and a drive circuit electrically connected to the pixel portion and having a second transistor, the first transistor comprises:
a first source electrode layer and a first drain electrode layer;
a first oxide semiconductor layer having regions in contact with top surfaces and side surfaces of the first source electrode layer and the first drain electrode layer; and
a first gate electrode layer over the first oxide semiconductor layer with a first gate insulating layer interposed therebetween,
the second transistor comprises:
a second gate electrode layer;
a second source electrode layer and a second drain electrode layer over the second gate electrode layer;
a second oxide semiconductor layer having regions in contact with top surfaces and side surfaces of the second source electrode layer and the second drain electrode layer; and
a third gate electrode layer over the second oxide semiconductor layer with a second gate insulating layer interposed therebetween,
wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise indium, gallium, and zinc.

2 . A semiconductor device comprising:
a pixel portion having a first transistor and a light-emitting element electrically connected to the first transistor; and a drive circuit electrically connected to the pixel portion and having a second transistor, the first transistor comprises:
a first insulating layer;
a first source electrode layer and a first drain electrode layer over the first insulating layer;
a first oxide semiconductor layer having regions in contact with top surfaces and side surfaces of the first source electrode layer and the first drain electrode layer; and
a first gate electrode layer over the first oxide semiconductor layer with a first gate insulating layer interposed therebetween,
the second transistor comprises:
a second gate electrode layer;
the first insulating layer over the second gate electrode layer;
a second source electrode layer and a second drain electrode layer over the first insulating layer;
a second oxide semiconductor layer having regions in contact with top surfaces and side surfaces of the second source electrode layer and the second drain electrode layer; and
a third gate electrode layer over the second oxide semiconductor layer with a second gate insulating layer interposed therebetween,
wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise indium, gallium, and zinc.

3 . The semiconductor device according to claim 2 , wherein the first insulating layer is a stack of silicon nitride and silicon oxide.

4 . The semiconductor device according to claim 1 , wherein the first gate electrode layer has a laminated structure and comprises an element selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum and copper.

5 . The semiconductor device according to claim 2 , wherein the first gate electrode layer has a laminated structure and comprises an element selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum and copper.

6 . The semiconductor device according to claim 1 , wherein the second gate electrode layer comprises an element selected from titanium, tantalum, tungsten, molybdenum and chromium.

7 . The semiconductor device according to claim 2 , wherein the second gate electrode layer comprises an element selected from titanium, tantalum, tungsten, molybdenum and chromium.

8 . The semiconductor device according to claim 1 , wherein the third gate electrode layer has a laminated structure and comprises an element selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum and copper.

9 . The semiconductor device according to claim 2 , wherein the third gate electrode layer has a laminated structure and comprises an element selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum and copper.

10 . The semiconductor device according to claim 1 , wherein the first source electrode layer, the first drain electrode layer, the second source electrode layer, and the second drain electrode layer each comprise aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten.

11 . The semiconductor device according to claim 2 , wherein the first source electrode layer, the first drain electrode layer, the second source electrode layer, and the second drain electrode layer each comprise aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Tsubuku Masashi
• Noda Kosei

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title