Display apparatus and driving method therefor

US2023410761A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023410761-A1
Application numberUS-202018037043-A
CountryUS
Kind codeA1
Filing dateNov 20, 2020
Priority dateNov 20, 2020
Publication dateDec 21, 2023
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display apparatus and a driving method therefor. The driving method includes: determining a gaze area and a non-gaze area of a user on a display apparatus in real time; and driving the gaze area for image displaying at a first resolution, and driving the non-gaze area for image displaying at a second resolution, wherein the first resolution is higher than the second resolution. By means of the display apparatus, image resolution can be adjusted according to different areas, so as to realize high-resolution image display in a display area at which a user gazes and realize low-resolution image display in other areas, thereby reducing power consumption and achieving reasonable allocation of resources on the premise of ensuring the user experience.

First claim

Opening claim text (preview).

1 . A display device, comprising: a substrate; a plurality of pixel islands located on the substrate, wherein the pixel island comprises a plurality of sub-pixels of different colors, the sub-pixels are arranged in an array in a first direction and a second direction, sub-pixels of the same color in one pixel island are arranged in a row in the first direction, sub-pixel rows of different colors are arranged in the second direction, and the first direction and the second direction intersect with each other; a plurality of data lines arranged in the first direction and extending in the second direction, wherein sub-pixels arranged in a same column in the second direction are connected to a same data line; a multiplexing circuit located in the second direction at a side of an area where the pixel islands are located, wherein the data lines are connected to the multiplexing circuit separately; a drive chip located in the second direction at a side, facing away from the pixel island, of the multiplexing circuit, wherein the multiplexing circuit is connected to the drive chip; a controller connected to the drive chip, and configured to provide a drive signal for the drive chip; and a microlens layer located at a side, facing away from the substrate, of the pixel island, the microlens layer modulating emergent light of the pixel island, so as to map the sub-pixels in the pixel island into a pixel array and implement three-dimensional display on same; wherein sub-pixel columns in one pixel island are divided into a plurality of sub-pixel groups in the first direction, and numbers of the sub-pixel columns in the sub-pixel groups are identical to each other; and the multiplexing circuit comprises a plurality of first multiplexing units arranged in the first direction, each of the first multiplexing units comprises one input end and a plurality of output ends, the first multiplexing units are connected to the sub-pixel groups in a one-to-one correspondence mode, the output ends of each of the first multiplexing units are connected to data lines corresponding to the sub-pixel groups respectively, and the input end of each of the first multiplexing units is connected to the drive chip. 2 . The display device according to claim 1 , the multiplexing circuit further comprises: a plurality of first-switch control signal lines extending in the first direction and arranged in the second direction; wherein each of the first multiplexing units comprises: a plurality of first-switch transistors, control poles of the first-switch transistors are connected to the first-switch control signal lines, first poles of the first-switch transistors are connected to the output ends of the each of the first multiplexing units, and second poles of the first-switch transistors are connected to the input end of the each of the first multiplexing units; and in each of the first multiplexing units, the control poles of the first-switch transistors are connected to different first-switch control signal lines respectively, and the first poles of the first-switch transistors are connected to different output ends of the each of the first multiplexing units respectively. 3 . The display device according to claim 2 , wherein the multiplexing circuit further comprises: a plurality of control units located in the second direction at a side, facing away from the pixel island, of the first multiplexing units, wherein the control units are arranged in the first direction, each of the control units comprises an input end and an output end, and the control units are connected to the first multiplexing units in a one-to-one correspondence mode; and the output end of each of the control units is connected to the input end of corresponding first multiplexing unit, and the input end of the each of the control units is connected to the drive chip. 4 . The display device according to claim 3 , wherein the multiplexing circuit further comprises: a control signal line extending in the first direction, wherein each of the control units comprises: a control switch transistor, a control pole of the control switch transistor is connected to the control signal line, a first pole of the control switch transistor is connected to the output end of the each of the control unit, and a second pole of the control switch transistor is connected to the input end of the each of the control unit. 5 . The display device according to claim 4 , wherein the multiplexing circuit further comprises: a plurality of second multiplexing units located in the second direction at the side, facing away from the pixel island, of the first multiplexing units, wherein the second multiplexing units are arranged in the first direction; each of the second multiplexing units comprises a plurality of input ends and a plurality of output ends, and a quantity of the input ends is less than a quantity of the output ends; and the second multiplexing units are connected to a plurality of pixel islands arranged in the first direction in a one-to-one correspondence mode, the output ends of the second multiplexing units are connected to data lines corresponding to the sub-pixel columns in the pixel islands respectively, and the input ends of the second multiplexing units are connected to the drive chip separately. 6 . The display device according to claim 5 , wherein the multiplexing circuit further comprises: a plurality of second-switch control signal lines extending in the first direction and arranged in the second direction; and a plurality of third-switch control signal lines extending in the first direction and arranged in the second direction, wherein each of the second multiplexing units comprises: a plurality of second-switch transistors and a plurality of third-switch transistors; a control pole of each of the second-switch transistors is connected to the second-switch control signal lines, a first pole of each of the second-switch transistors is connected to the output end of each of the second multiplexing units, a second pole of each of the second-switch transistors is connected to a first pole of each of the third-switch transistors, a control pole of each of the third-switch transistors is connected to the third-switch control signal lines, and a second pole of each of the third-switch transistors is connected to the input end of each of the second multiplexing units; in each of the second multiplexing units, control poles of second-switch transistors connected to a same pixel island are connected to a same second-switch control signal line, control poles of second-switch transistors connected to different pixel islands are connected to different second-switch control signal lines, and second poles of second-switch transistors connected to sub-pixel columns at a same position in the pixel islands are connected to each other; in each of the second multiplexing units, the third-switch transistors correspond to one of pixel islands connected to each of the second multiplexing units, and in the third-switch transistors and second-switch transistors corresponding to the pixel island, first poles of the third-switch transistors are connected to second poles of the second-switch transistors respectively; in each of the second multiplexing units, the third-switch transistors are divided into a plurality of third-switch transistor groups in the first direction, and a quantity of the third-switch transistor groups equals a quantity of sub-pixel groups comprised in one pixel island; and in each of the third-switch transistor groups, control poles of the third-switch transistors are connected to different third-switch control signal lines respectively, and second poles of the third-switch transistors are connected to a same input end of each of the second multiplexing units.

Assignees

Inventors

Classifications

  • G09G3/3674Primary

    Details of drivers for scan electrodes · CPC title

  • for tracking with gaze detection, i.e. detecting the lines of sight of the viewer's eyes · CPC title

  • Three-dimensional [3D] image rendering · CPC title

  • Aspects of interface with display user · CPC title

  • H04N13/305Primary

    using lenticular lenses, e.g. arrangements of cylindrical lenses · CPC title

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What does patent US2023410761A1 cover?
A display apparatus and a driving method therefor. The driving method includes: determining a gaze area and a non-gaze area of a user on a display apparatus in real time; and driving the gaze area for image displaying at a first resolution, and driving the non-gaze area for image displaying at a second resolution, wherein the first resolution is higher than the second resolution. By means of th…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3674. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Dec 21 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).