Programmable memory and method for driving programmable memory

Patent metadata

Field	Value
Publication number	US-2023402118-A1
Application number	US-202318155692-A
Country	US
Kind code	A1
Filing date	Jan 17, 2023
Priority date	Jun 14, 2022
Publication date	Dec 14, 2023
Grant date	—

Abstract

A programmable memory includes a plurality of antifuse cells, a plurality of word lines and a control circuit. The plurality of antifuse cells are arrayed along row and column directions, herein each of the plurality of antifuse cells includes an antifuse and a switching transistor, a first end of the antifuse being connected to a first terminal of the switching transistor. Each of the plurality of word lines is connected to gates of the switching transistors located in a same row. The control circuit is connected to the plurality of word lines, and is configured to provide a first voltage to a word line connected to a target antifuse cell in a program mode, and provide a second voltage to the word line connected to the target antifuse cell in a read mode, herein the first voltage is greater than the second voltage.

First claim

What is claimed is:

1 . A programmable memory, comprising:
a plurality of antifuse cells, arrayed along row and column directions, wherein each of the plurality of antifuse cells comprises an antifuse and a switching transistor, a first end of the antifuse being connected to a first terminal of the switching transistor; a plurality of word lines, wherein each of the plurality of word lines is connected to gates of the switching transistors located in a same row; and a control circuit, connected to the plurality of word lines, and configured to provide a first voltage to a word line connected to a target antifuse cell in a program mode, and provide a second voltage to the word line connected to the target antifuse cell in a read mode, wherein the first voltage is greater than the second voltage.

2 . The programmable memory of claim 1 , further comprising:
a plurality of bit lines, wherein each of the plurality of bit lines is connected to second terminals of the switching transistors located in a same column; and a precharge circuit, connected to the plurality of bit lines, and configured to provide a precharge voltage to the plurality of bit lines in the program mode.

3 . The programmable memory of claim 2 , wherein the precharge circuit comprises:
a plurality of first switches arranged in one-to-one correspondence with the plurality of bit lines, wherein the first switch has a first end connected to a bit line corresponding to the first switch, a second end configured to receive the precharge voltage, and a control end connected to a precharge signal end, the precharge signal end being for outputting an effective level in the program mode.

4 . The programmable memory of claim 2 , further comprising:
a column selection circuit, connected to the plurality of bit lines, and configured to pull down, according to a column selection signal, a voltage of a bit line connected to the target antifuse cell in the program mode.

5 . The programmable memory of claim 4 , wherein the column selection circuit comprises:
a plurality of second switches arranged in one-to-one correspondence with the plurality of bit lines, wherein the second switch has a first end connected to a bit line corresponding to the second switch, a second end configured to receive a low-level voltage, and a control end configured to receive the column selection signal.

6 . The programmable memory of claim 1 , wherein the control circuit comprises:
a plurality of word line control circuits arranged in one-to-one correspondence with the plurality of word lines, wherein the word line control circuit is configured to transmit, according to a word line address signal, a power supply voltage to the word line connected to the target antifuse cell; and a voltage regulating circuit, configured to provide the power supply voltage to the word line control circuits, wherein the power supply voltage is the first voltage in the program mode, and the power supply voltage is the second voltage in the read mode.

7 . The programmable memory of claim 6 , wherein the word line address signal comprises a first address signal and a second address signal, and the word line control circuit comprises:
a first N-type transistor, wherein a first terminal of the first N-type transistor is grounded, and a gate of the first N-type transistor is configured to receive the first address signal; a second N-type transistor, wherein a first terminal of the second N-type transistor is connected to a second terminal of the first N-type transistor, a second terminal of the second N-type transistor is connected to a first node, and a gate of the second N-type transistor is configured to receive the second address signal; a third N-type transistor, wherein a first terminal of the third N-type transistor is grounded, a second terminal of the third N-type transistor is connected to a word line corresponding to the word line control circuit, and a gate of the third N-type transistor is connected to the first node; a fourth P-type transistor, wherein a first terminal of the fourth P-type transistor is configured to receive the power supply voltage, a second terminal of the fourth P-type transistor is connected to the word line corresponding to the word line control circuit, and a gate of the fourth P-type transistor is connected to the first node; a fifth P-type transistor, wherein a first terminal of the fifth P-type transistor is configured to receive the power supply voltage, a second terminal of the fifth P-type transistor is connected to the first node, and a gate of the fifth P-type transistor is configured to receive the first address signal; and a sixth P-type transistor, wherein a first terminal of the sixth P-type transistor is configured to receive the power supply voltage, a second terminal of the sixth P-type transistor is connected to the first node, and a gate of the sixth P-type transistor is configured to receive the second address signal.

8 . The programmable memory of claim 7 , wherein the first address signal is a row address signal, and the second address signal is a subarray address signal.

9 . The programmable memory of claim 6 , wherein the voltage regulating circuit comprises:
a comparator, wherein an inverting input end of the comparator is configured to receive a reference voltage, a non-inverting input end of the comparator is connected to a second node, and an output end of the comparator is connected to a third node; a seventh P-type transistor, wherein a first terminal of the seventh P-type transistor is connected to a power supply end, a second terminal of the seventh P-type transistor is configured to output the power supply voltage, and a gate of the seventh P-type transistor is connected to the third node; a first variable resistor, connected between the second terminal of the seventh P-type transistor and the second node; a second variable resistor, connected between the second node and a ground end; and an adjusting circuit, configured to adjust, according to a program flag signal, at least one of the reference voltage, the first variable resistor, or the second variable resistor.

10 . The programmable memory of claim 6 , wherein the voltage regulating circuit comprises:
a control signal generation circuit, configured to output, according to a program flag signal, a first control signal or a second control signal; and a voltage selection circuit, configured to:
receive the first control signal or the second control signal; and
output, according to the first control signal, the first voltage to the word line control circuits, or output, according to the second control signal, the second voltage to the word line control circuits.

11 . The programmable memory of claim 10 , wherein the control signal generation circuit comprises:
an eighth N-type transistor, wherein a first terminal of the eighth N-type transistor is connected to a low-level signal end, a gate of the eighth N-type transistor is configured to receive the program flag signal, and a second terminal of the eighth N-type transistor is configured to output the first control signal; an inverter, wherein an input end of the inverter is configured to receive the program flag signal; a ninth N-type transistor, wherein a first terminal of the ninth N-type transistor is connected to a high-level signal end, a gate of the ninth N-type transistor is connected to an output end of the inverter, and a second terminal of the ninth N-type transistor is connected to the second terminal of the eighth N-type transistor; a tenth N-type transistor, wherein a first terminal of the tenth N-type transistor is connected to the low-level signal end, a gat

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Rumin

Classifications

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C17/16 Primary

  using electrically-fusible links · CPC title