Planar complementary mosfet structure to reduce leakages and planar areas

Patent metadata

Field	Value
Publication number	US-2023397411-A1
Application number	US-202318203688-A
Country	US
Kind code	A1
Filing date	May 31, 2023
Priority date	Jun 2, 2022
Publication date	Dec 7, 2023
Grant date	—

Abstract

The present invention discloses a planar CMOSFET structure used in the peripheral circuit of DRAM chip and in sense amplifiers of array core circuit of DRAM chip, the planar CMOSFET structure comprises a planar P type MOSFET with a first conductive region, a planar N type MOSFET with a second conductive region, and a cross-shape localized isolation region between the planar P type MOSFET and the planar N type MOSFET; wherein the cross-shape localized isolation region includes a horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.

First claim

What is claimed is:

1 . A DRAM circuit, comprising:
a semiconductor substrate with a semiconductor surface; an array core circuit with a sense amplifier circuit and a plurality of DRAM cells electrically coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit, wherein either the sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, the complementary MOSFET structure comprising:
a planar P type MOSFET comprising a first conductive region;
a planar N type MOSFET comprising a second conductive region;
a cross-shape localized isolation region between the planar P type MOSFET and the planar N type MOSFET, wherein the cross-shape localized isolation region includes a horizontally extended isolation region below the semiconductor surface, and the horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.

2 . The DRAM circuit in claim 1 , wherein the complementary MOSFET structure further comprises a first concave formed below the semiconductor surface, and the first concave accommodates the first conductive region.

3 . The DRAM circuit in claim 2 , wherein the first conductive region comprises an undoped semiconductor region and/or a lightly doped semiconductor region, and the first conductive region is independent from the semiconductor substrate.

4 . The DRAM circuit in claim 3 , wherein the undoped semiconductor region or the lightly doped semiconductor region abuts against a channel region of the planar P type MOSFET.

5 . The DRAM circuit in claim 3 , the first conductive region further comprising a heavily doped semiconductor region, wherein the heavily doped semiconductor region is positioned in the first concave, and the lightly doped semiconductor region and the heavily doped semiconductor region are formed with same lattice structure.

6 . The DRAM circuit in claim 5 , wherein the first conductive region further comprising a metal region, the metal region is positioned in the first concave and abuts against the heavily doped semiconductor region.

7 . The DRAM circuit in claim 1 , wherein the complementary MOSFET structure further comprises a first concave formed below the semiconductor surface, the first concave accommodates a first portion of the horizontally extended isolation region.

8 . The DRAM circuit in claim 7 , wherein the planar P type MOSFET further comprises a gate region over the semiconductor surface, and an edge of the gate region is aligned or substantially aligned with an edge of the first conductive region.

9 . The DRAM circuit in claim 7 , wherein the planar P type MOSFET further comprises a gate region, and all of the first portion of the horizontally extended isolation region is not directly underneath the gate structure.

10 . The DRAM circuit in claim 7 , wherein the planar P type MOSFET further comprises a gate region, and less than 5% of the first portion of the horizontally extended isolation region is directly underneath the gate structure.

11 . The DRAM circuit in claim 1 , wherein the horizontally extended isolation region is a composite isolation region.

12 . The DRAM circuit in claim 11 , wherein the composite isolation region includes an oxide layer and a nitride layer over the oxide layer.

13 . The DRAM circuit in claim 1 , wherein the horizontally extended isolation region includes a first horizontally extended isolation region and a second horizontally extended isolation region, the bottom side of the first conductive region is shielded from the semiconductor substrate by the first horizontally extended isolation region, and the bottom side of the second conductive region is shielded from the semiconductor substrate by the second horizontally extended isolation region.

14 . A DRAM circuit, comprising:
a semiconductor substrate with a semiconductor surface; an array core circuit with a sense amplifier circuit and a plurality of DRAM cells coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit, wherein either the sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, the complementary MOSFET structure comprising:
a planar P type MOSFET comprising a first source region, a first drain region, and a first gate region over the semiconductor surface;
a planar N type MOSFET comprising a second source region, a second drain region, and a second gate region over the semiconductor surface;
wherein the first source region or the first drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region laterally abutted against the lightly doped semiconductor region;
wherein one DRAM cell includes an access transistor and a storage capacitor, the access transistor comprises a third source region, a third drain region, and a third gate region, and the third source region or the third drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region vertically abutted against the lightly doped semiconductor region.

15 . The DRAM circuit in claim 14 , wherein the DRAM circuit is formed by a technology node λ, wherein a gate length of the first gate region is between 1.5λ˜3λ, and Δ is between 12 nm˜30 nm.

16 . The DRAM circuit in claim 14 , wherein one edge of the first gate region is aligned or substantially aligned with an edge of the first source region, and another edge of the first gate region is aligned or substantially aligned with an edge of the first drain region.

17 . The DRAM circuit in claim 14 , the complementary MOSFET structure further comprising a localized isolation region between the planar P type MOSFET and the planar N type MOSFET, and a highly doped P+ region in the first source region or the first drain region is shielded from the semiconductor substrate by the localized isolation region.

18 . The DRAM circuit in claim 17 , wherein the localized isolation region includes a vertically extended isolation region and a horizontally extended isolation region, and a latch-up path between the planar P type MOSFET and the planar N type MOSFET is at least dependent on a bottom length of the horizontally extended isolation region.

19 . A DRAM circuit, comprising:
a semiconductor substrate with a semiconductor surface; an array core circuit with a sense amplifier circuit and a plurality of DRAM cells electrically coupled to the sense amplifier circuit, each DRAM cell includes an access transistor and a storage capacitor; and a peripheral circuit electrically coupled to the array core circuit, wherein either the sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, the complementary MOSFET structure comprising:
a planar P type MOSFET comprising a first selectively grown source region, a first selectively grown drain region, and a first gate region over the semiconductor surface; and
a planar N type MOSFET comprising a second selectively grown source region, a second selectively grown drain region, and a second gate region over the semiconductor surface;
wherein the access transistor comprises a third source region, a third drain region, and a third gate region, at least portion of the third gate region is under the semiconductor surface; wherein the first selectively grown source region or the first selectively grown drain region includes a bottom surface lower than a bottom surface of the first g

Assignees

• Invent And Collaboration Laboratory Pte Ltd

Inventors

• Lu chao-chun
• Huang Li-Ping

Classifications

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D84/854

  comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title