Logic circuit and semiconductor device

Patent metadata

Field	Value
Publication number	US-2023395726-A1
Application number	US-202318237431-A
Country	US
Kind code	A1
Filing date	Aug 24, 2023
Priority date	Oct 16, 2009
Publication date	Dec 7, 2023
Grant date	—

Abstract

A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×10 19 (atoms/cm 3 ) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

First claim

1 . (canceled)

2 . A light-emitting device comprising:
a display portion, the display portion comprising:
a light-emitting element; and
a first transistor electrically connected to a first electrode of the light-emitting element, the first transistor comprising:
a first gate electrode layer over a substrate and a first insulating layer;
a second insulating layer over the first gate electrode layer;
an oxide semiconductor layer over the second insulating layer;
a first wiring layer electrically connected to the oxide semiconductor layer via a first opening provided in a third insulating layer;
a second wiring layer electrically connected to the oxide semiconductor layer via a second opening provided in the third insulating layer; and
a second gate electrode layer over the third insulating layer,

wherein the first transistor is provided below the first electrode of the light-emitting element, wherein the third insulating layer is provided over and in contact with the oxide semiconductor layer, wherein the second gate electrode layer overlaps with the oxide semiconductor layer and the first gate electrode layer, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the first gate electrode layer and the second gate electrode layer are electrically connected to each other, wherein, in a cross-sectional view, the first wiring layer and the second wiring layer do not overlap with the first gate electrode layer and the second gate electrode layer, wherein the first electrode of the light-emitting element overlaps with a channel formation region of the first transistor, and wherein the oxide semiconductor layer is an island-shaped layer.

3 . A light-emitting device comprising:
a display portion, the display portion comprising:
a light-emitting element; and
a first transistor electrically connected to a first electrode of the light-emitting element, the first transistor comprising:
a first gate electrode layer over a substrate;
a first insulating layer over the first gate electrode layer;
an oxide semiconductor layer over the first insulating layer;
a first wiring layer electrically connected to the oxide semiconductor layer via a first opening provided in a second insulating layer;
a second wiring layer electrically connected to the oxide semiconductor layer via a second opening provided in the second insulating layer; and
a second gate electrode layer over the second insulating layer,

wherein the first transistor is provided below the first electrode of the light-emitting element, wherein the second insulating layer is provided over and in contact with the oxide semiconductor layer, wherein the second gate electrode layer overlaps with the oxide semiconductor layer and the first gate electrode layer, wherein the first gate electrode layer and the second gate electrode layer are electrically connected to each other, wherein, in a cross-sectional view, the first wiring layer and the second wiring layer do not overlap with the first gate electrode layer and the second gate electrode layer, wherein the first electrode of the light-emitting element overlaps with a channel formation region of the first transistor, and wherein the oxide semiconductor layer is an island-shaped layer.

4 . A light-emitting device comprising:
a first transistor, the first transistor comprising:
a first gate electrode layer over a substrate;
a first insulating layer over the first gate electrode layer; and
an oxide semiconductor layer over the first insulating layer.

5 . The light-emitting device according to claim 4 ,
wherein the first transistor further comprises:
a first wiring layer electrically connected to the oxide semiconductor layer via a first opening provided in a second insulating layer;
a second wiring layer electrically connected to the oxide semiconductor layer via a second opening provided in the second insulating layer; and
a second gate electrode layer over the second insulating layer,
wherein the second insulating layer is provided over and in contact with the oxide semiconductor layer, wherein the second gate electrode layer overlaps with the oxide semiconductor layer and the first gate electrode layer, wherein the first gate electrode layer and the second gate electrode layer are connected to each other, wherein, in a cross-sectional view, the first wiring layer and the second wiring layer do not overlap with the first gate electrode layer and the second gate electrode layer, wherein the oxide semiconductor layer is an island-shaped layer, wherein the oxide semiconductor layer comprises a crystalline portion, and wherein a grain diameter of the crystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Tsubuku Masashi
• Noda Kosei

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title