Pre-Sense Gut Node Amplification in Sense Amplifier

Patent metadata

Field	Value
Publication number	US-2023395130-A1
Application number	US-202217829737-A
Country	US
Kind code	A1
Filing date	Jun 1, 2022
Priority date	Jun 1, 2022
Publication date	Dec 7, 2023
Grant date	—

Abstract

A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

First claim

1 . A memory device, comprising:
a plurality of memory cells configured to store data; a plurality of digit lines each configured to carry data to and from a respective memory cell of the plurality of memory cells; and a plurality of sense amplifiers each selectively coupled to respective digit lines of the plurality of digit lines and comprising first and second NMOS transistors and first and second gut nodes that are respectively coupled to the first and second NMOS transistors, wherein each sense amplifier is configured to:
charge a first voltage on the first gut node that at least partially compensates for threshold voltage fluctuations of the first NMOS transistor due to process, voltage, or temperature fluctuations and is proportional to the threshold voltage of the first NMOS transistor;
charge a second voltage on the second gut node that at least partially compensates for threshold voltage fluctuations of the second NMOS transistor due to process, voltage, or temperature fluctuations and is proportional to the threshold voltage of the second NMOS transistor;
amplify a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges from the plurality of digit lines; and
send the amplified differential voltage to respective digit lines of the plurality of digit lines as a differential signal.

2 . The memory device of claim 1 , wherein the plurality of digit lines comprise a plurality of complementary pairs of the digit lines of the plurality of digit lines.

3 . The memory device of claim 2 , wherein each digit line of each of the plurality of complementary pairs of the digit lines is coupled to respective memory cells storing complementary data.

4 . The memory device of claim 1 , wherein the sense amplifier comprises a first digit line of the plurality of digit lines that corresponds to the first gut node and a second digit line of the plurality of digit lines corresponds to the second gut node.

5 . The memory device of claim 4 , wherein the sense amplifier comprises an equalization transistor configured to equalize the first and second gut node before amplifying the differential voltage.

6 . The memory device of claim 5 , wherein equalization of the first and second gut nodes comprises receiving a logic voltage from a respective memory cell of the plurality of memory cells to charge the first digit line that causes the second gut node to be discharged, wherein the discharge of the second gut node causes the first gut node to be charged using a supply voltage, wherein the equalization via the equalization transistor is performed after the first gut node is charged.

7 . The memory device of claim 6 , wherein the sense amplifier comprises cross-coupled PMOS transistors, and wherein the charging of first gut node uses the discharging of the second gut node via the cross-coupled PMOS transistors to charge the first gut node.

8 . The memory device of claim 7 , where the charging of the first gut node in the differential amplification is performed via the cross-coupled PMOS transistors with the equalizing transistor decoupling the first and second gut nodes and the second NMOS transistor discharging of the second gut node.

9 . The memory device of claim 1 , wherein the memory device is operating in low-voltage operation during the charging of the first voltage, charging of the second voltage, amplification of the differential voltage, and sending the amplified differential voltage to the respective digit lines.

10 . The memory device of claim 1 , wherein the first and second NMOS transistors are coupled to a plurality of transistors between the first and second NMOS transistors and ground.

11 . The memory device of claim 10 , wherein at least two of the plurality of transistors are toggled at different times.

12 . A memory device, comprising:
one or more memory cells configured to store data; a pair of digit lines coupled to the one or more memory cells; and a sense amplifier coupled to the pair of digit lines and comprising:
cross-coupled transistors coupled to a supply voltage;
a first gut node coupled to a first transistor of the cross-coupled transistors, wherein the first gut node corresponds to a first digit line of the pair of digit lines;
a second gut node coupled to a second transistor of the cross-coupled transistors, wherein the second gut node corresponds to a second digit line of the pair of digit lines;
a third transistor coupled to the first gut node, wherein a gate of the third transistor is coupled to the second digit line;
a fourth transistor coupled to the second gut node, where a gate of the fourth transistor is coupled to the first digit line;
a first isolating transistor coupled between the first digit line and the first gut node to selectively decouple the first digit line from the first gut node when amplifying a difference in voltages between the first and second gut nodes; and
a second isolating transistor coupled between the second digit line and the second gut node to selectively decouple the second digit line from the second gut node when amplifying the difference in voltages between the first and second gut nodes.

13 . The memory device of claim 12 , wherein the first and second transistors comprise PMOS transistors.

14 . The memory device of claim 12 , wherein the first digit line is configured to be charged using a logic high value stored in a cell of the one or more memory cells.

15 . The memory device of claim 14 , wherein the fourth transistor is configured to use the charge of the first digit line to discharge a voltage stored in the second gut node.

16 . The memory device of claim 15 , wherein the first transistor is configured to use the discharged voltage of the second gut node to amplify the voltage of first gut node to amplify a differential voltage between the first and second gut nodes.

17 . The memory device of claim 12 , wherein the sense amplifier comprises:
a first compensation transistor coupled between the gate of the third transistor and a source of the third transistor to charge the first gut node with a first voltage proportional to a threshold voltage of the third transistor during a threshold voltage compensation phase; and a second compensation transistor coupled between the gate of the fourth transistor and a source of the fourth transistor to charge the second gut node with a second voltage proportional to a threshold voltage of the fourth transistor during the threshold voltage compensation phase.

18 . A method comprising:
configuring a first transistor of a sense amplifier for a memory device in a first diode configuration using a first compensation transistor to couple gate and source terminals of the first transistor together to charge a first gut node with a first voltage proportional to a first threshold voltage of the first transistor; configuring a second transistor of the sense amplifier in a second diode configuration using a second compensation transistor to couple gate and source terminals of the second transistor together to charge a second gut node with a second voltage proportional to a second threshold voltage of the second transistor; disconnecting the gate terminal from the source terminal of the first transistor using the first compensation transistor; disconnecting the gate terminal from the source terminal of the second transistor using the second compensation transistor; using the sense amplifier, amplifying a difference in voltages

Assignees

• Micron Technology Inc

Inventors

• Vo Huy T
• Morzano Christopher K
• Kawamura Christopher J
• Ingalls Charles L

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title