Silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-2023387291-A1
Application number	US-202318193750-A
Country	US
Kind code	A1
Filing date	Mar 31, 2023
Priority date	May 26, 2022
Publication date	Nov 30, 2023
Grant date	—

Abstract

A semiconductor device having, in an outer peripheral portion of an active region, and in a depth direction from a front surface of a semiconductor substrate, first to fourth outer peripheral regions, to thereby form steps that are recessed stepwise toward the center of the semiconductor device by a same width, and are arranged in an ascending order of the proximity to the center in the depth direction. The first, second, and fourth outer peripheral regions, respectively, are formed concurrently with p ++ -type contact regions, a p-type base region, and lower portions of p + -type regions in a center portion of the active region. An impurity concentration of the third outer peripheral region is 0.1 times to 0.5 times the impurity concentration of the upper portions of the p + -type regions. A voltage withstanding structure is formed in contact with an outer end of the first outer peripheral region.

First claim

What is claimed is:

1 . A silicon carbide semiconductor device, comprising:
a semiconductor substrate containing silicon carbide and having a first main surface and a second main surface that are opposite to each other, an entire area of the first main surface being flat, the semiconductor substrate having, in a plan view of the silicon carbide semiconductor device,
an active region at a center of the semiconductor substrate, and
a termination region that surrounds a periphery of the active region;
a first semiconductor region of a first conductivity type, provided in the semiconductor substrate, and spanning the active region and the termination region; a second semiconductor region of a second conductivity type, provided in the semiconductor substrate, between the first main surface and the first semiconductor region and in the active region; a device structure having a pn junction between the first semiconductor region and the second semiconductor region, a current that passes through the pn junction flowing through the device structure; a second-conductivity-type outer peripheral region formed at the periphery of the active region, the second-conductivity-type outer peripheral region being provided between the first main surface and the first semiconductor region, and between the device structure and the termination region; a voltage withstanding structure configured by a plurality of second-conductivity-type voltage withstanding regions, provided between the first main surface and the first semiconductor region and in the termination region, the plurality of second-conductivity-type voltage withstanding regions being provided apart from one another in a width direction that is parallel to the first main surface, in concentric shapes surrounding the periphery of the active region; a plurality of first electrodes electrically connected to the second semiconductor region and the second-conductivity-type outer peripheral region, the plurality of first electrodes being provided at the first main surface; and a second electrode electrically connected to the first semiconductor region, the second electrode being provided on the second main surface of the semiconductor substrate, wherein the device structure has: a third semiconductor region of the first conductivity type, selectively provided in the semiconductor substrate and between the first main surface and the second semiconductor region, the third semiconductor region being electrically connected to the plurality of first electrodes,
a trench penetrating through the third semiconductor region and the second semiconductor region, and reaching the first semiconductor region,
a gate electrode provided in the trench via a gate insulating film, and
a plurality of second-conductivity-type high-concentration regions, selectively provided in the semiconductor substrate and between the first semiconductor region and the second semiconductor region, so as to be closer to the second main surface of the semiconductor substrate than is a bottom of the trench, the plurality of second-conductivity-type high-concentration regions having an impurity concentration that is higher than an impurity concentration of the second semiconductor region; and
the second-conductivity-type outer peripheral region has a plurality of outer peripheral regions that include:
a first outer peripheral region closest to the first main surface and in contact with an inner end of the voltage withstanding structure, the first outer peripheral region having a first surface and a second surface that are opposite to each other, the second surface of the first outer peripheral region facing the second main surface of the semiconductor substrate,
a second outer peripheral region that is a portion of the second semiconductor region, and that is closer to an end of the semiconductor substrate than is the device structure, the second outer peripheral region being adjacent to the second surface of the first outer peripheral region, and having a first surface and a second surface that are opposite to each other, the second surface of the second outer peripheral region facing the second main surface of the semiconductor substrate,
a third outer peripheral region adjacent to the second surface of the second outer peripheral region, and having a first surface and a second surface that are opposite to each other, the second surface of the third outer peripheral region facing the second main surface of the semiconductor substrate, and
a fourth outer peripheral region adjacent to the second surface of the third outer peripheral region, a lower surface of the fourth outer peripheral region and a lower surface of each of the plurality of second-conductivity-type high-concentration regions being at a same depth,
the first to fourth outer peripheral regions being arranged to form, at an outer end of the second-conductivity-type outer peripheral region, a plurality of steps that are recessed stepwise toward the center of the semiconductor substrate, so as to be in an ascending order of proximity to the center, in a depth direction from the first main surface to the second main surface of the semiconductor substrate, each of the plurality of steps having a same width in the width direction.

2 . The silicon carbide semiconductor device according to claim 1 , wherein
an impurity concentration of the third outer peripheral region is lower than the impurity concentration of the plurality of second-conductivity-type high-concentration regions.

3 . The silicon carbide semiconductor device according to claim 2 , wherein
the impurity concentration of the third outer peripheral region is within a range of 0.1 times to 0.5 times the impurity concentration of the plurality of second-conductivity-type high-concentration regions.

4 . The silicon carbide semiconductor device according to claim 1 , wherein
an impurity concentration of the fourth outer peripheral region is equal to the impurity concentration of the plurality of second-conductivity-type high-concentration regions.

5 . The silicon carbide semiconductor device according to claim 1 , wherein
the width of the plurality of steps at the outer end of the second-conductivity-type outer peripheral region is in a range of 1 μm to 4 μm.

6 . The silicon carbide semiconductor device according to claim 1 , wherein
the plurality of second-conductivity-type high-concentration regions includes:
a first second-conductivity-type high-concentration region selectively provided in the semiconductor substrate and between the first semiconductor region and the second semiconductor region, the first second-conductivity-type high-concentration region facing the bottom of the trench and having an impurity concentration that is higher than the impurity concentration of the second semiconductor region, and
a second second-conductivity-type high-concentration region selectively provided in the semiconductor substrate and between the first semiconductor region and the second semiconductor region, so as to be in contact with the second semiconductor region while being apart from the trench and the first second-conductivity-type high-concentration region, the second second-conductivity-type high-concentration region being closer to the second main surface than is the bottom of the trench, and having an upper surface and a lower surface, a lower portion of the second second-conductivity-type high-concentration region facing the second main surface, an impurity concentration of the second second-conductivity-type high-concentration region being higher than the impurity concentration of the second semiconductor region;
the first surface of the third outer peripheral region and the upper surface of second second-conductivity-type high-concentration r

Assignees

• Fuji Electric Co Ltd

Inventors

• Hoshi Yasuyuki

Classifications

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/109

  Reduced surface field [RESURF] PN junction structures · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/665 Primary

  having edge termination structures · CPC title