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US-2024414942-A1 · Dec 12, 2024 · US
Method for manufacturing oxide semiconductor device
US2023387136A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2023387136-A1 |
| Application number | US-202318231902-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 9, 2023 |
| Priority date | Jul 31, 2009 |
| Publication date | Nov 30, 2023 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
First claim
Opening claim text (preview).
1 . (canceled) 2 . A semiconductor device comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and a first wiring, a second wiring, and a third wiring, wherein one of a source and a drain of the first transistor is electrically connected to a second output terminal, wherein one of a source and a drain of the second transistor is electrically connected to the second output terminal, wherein the other of the source and the drain of the first transistor is electrically connected to the to the first wiring, wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring, wherein one of a source and a drain of the third transistor is electrically connected to a first output terminal, wherein one of a source and a drain of the fourth transistor is electrically connected to the first output terminal, wherein a gate of the fourth transistor is electrically connected to a first gate of the fifth transistor, a second gate of the fifth transistor, and a gate of the sixth transistor, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the seventh transistor, and wherein a gate of the seventh transistor is electrically connected to the third wiring. 3 . A semiconductor device comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and a first wiring, a second wiring, and a third wiring, wherein one of a source and a drain of the first transistor is electrically connected to a second output terminal, wherein one of a source and a drain of the second transistor is electrically connected to the second output terminal, wherein the other of the source and the drain of the first transistor is electrically connected to the to the first wiring, wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring, wherein one of a source and a drain of the third transistor is electrically connected to a first output terminal, wherein one of a source and a drain of the fourth transistor is electrically connected to the first output terminal, wherein a gate of the fourth transistor is electrically connected to a first gate of the fifth transistor, a second gate of the fifth transistor, and a gate of the sixth transistor, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein a gate of the seventh transistor is electrically connected to the third wiring, and wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fifth transistor. 4 . A semiconductor device comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and a first wiring, a second wiring, and a third wiring, wherein one of a source and a drain of the first transistor is electrically connected to a second output terminal, wherein one of a source and a drain of the second transistor is electrically connected to the second output terminal, wherein the other of the source and the drain of the first transistor is electrically connected to the to the first wiring, wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring, wherein one of a source and a drain of the third transistor is electrically connected to a first output terminal, wherein one of a source and a drain of the fourth transistor is electrically connected to the first output terminal, wherein a gate of the fourth transistor is electrically connected to a first gate of the fifth transistor, a second gate of the fifth transistor, and a gate of the sixth transistor, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein a gate of the seventh transistor is electrically connected to the third wiring, wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fifth transistor, wherein the fifth transistor comprises an oxide semiconductor in a channel formation region, and wherein the third transistor comprises an oxide semiconductor in a channel formation region.
Assignees
Inventors
Classifications
- H10D30/6755Primary
Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title
- H10D86/441Primary
Interconnections, e.g. scanning lines · CPC title
- H10D86/60Primary
wherein the TFTs are in active matrices · CPC title
characterised by the compositions or shapes of the interlayer dielectrics · CPC title
characterised by multiple TFTs · CPC title
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Frequently asked questions
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- What does patent US2023387136A1 cover?
- An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering …
- Who is the assignee on this patent?
- Semiconductor Energy Lab
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Nov 30 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).