Wiring substrate

Patent metadata

Field	Value
Publication number	US-2023380055-A1
Application number	US-202318307131-A
Country	US
Kind code	A1
Filing date	Apr 26, 2023
Priority date	May 19, 2022
Publication date	Nov 23, 2023
Grant date	—

Abstract

A wiring substrate includes a core substrate, a build-up part formed on a surface of the substrate and including insulating layers and conductor layers, and a covering insulating layer formed on the build-up part such that the covering layer is covering the outermost surface of the build-up part. The build-up part is formed such that the insulating layers include a first insulating layer forming the outermost one of the insulating layers, that the conductor layers include a first conductor layer formed on the first insulating layer and including a first conductor pad, and that a tensile strength of the first insulating layer is higher than a tensile strength of each insulating layer other than the first insulating layer in the first build-up part, and the covering layer is formed such that the covering layer has opening entirely exposing an upper surface and a side surface of the first conductor pad.

First claim

1 . A wiring substrate, comprising:
a core substrate; a build-up part formed on a surface of the core substrate and comprising a plurality of insulating layers and a plurality of conductor layers; and a covering insulating layer formed on the build-up part such that the covering insulating layer is covering an outermost surface of the build-up part, wherein the build-up part is formed such that the plurality of insulating layers includes a first insulating layer forming an outermost one of the insulating layers, that the plurality of conductor layers includes a first conductor layer formed on the first insulating layer and including a first conductor pad, and that a tensile strength of the first insulating layer is higher than a tensile strength of each of the insulating layers other than the first insulating layer in the build-up part, and the covering insulating layer is formed such that the covering insulating layer has an opening entirely exposing an upper surface and a side surface of the first conductor pad.

2 . The wiring substrate according to claim 1 , wherein the build-up part is formed such that the first conductor pad of the first conductor layer is not directly connected to another pad in the first conductor layer or a wiring in the first conductor layer.

3 . The wiring substrate according to claim 1 , wherein the build-up part is formed such that the tensile strength of the first insulating layer is 125 MPa or greater.

4 . The wiring substrate according to claim 1 , wherein the build-up part is formed such that the first insulating layer has a dielectric loss tangent of 0.013 or less at a frequency of 5.8 GHz.

5 . The wiring substrate according to claim 1 , further comprising:
a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part.

6 . The wiring substrate according to claim 5 , wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material.

7 . The wiring substrate according to claim 1 , wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer.

8 . The wiring substrate according to claim 2 , wherein the build-up part is formed such that the tensile strength of the first insulating layer is 125 MPa or greater.

9 . The wiring substrate according to claim 2 , wherein the build-up part is formed such that the first insulating layer has a dielectric loss tangent of 0.013 or less at a frequency of 5.8 GHz.

10 . The wiring substrate according to claim 2 , further comprising:
a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part.

11 . The wiring substrate according to claim 10 , wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material.

12 . The wiring substrate according to claim 2 , wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer.

13 . The wiring substrate according to claim 3 , wherein the build-up part is formed such that the first insulating layer has a dielectric loss tangent of 0.013 or less at a frequency of 5.8 GHz.

14 . The wiring substrate according to claim 3 , further comprising:
a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part.

15 . The wiring substrate according to claim 14 , wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material.

16 . The wiring substrate according to claim 3 , wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer.

17 . The wiring substrate according to claim 4 , further comprising:
a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part.

18 . The wiring substrate according to claim 17 , wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material.

19 . The wiring substrate according to claim 4 , wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer.

20 . The wiring substrate according to claim 5 , wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer.

Assignees

• Ibiden Co Ltd

Inventors

• Kato Masataka
• Sakai Shunsuke
• Tawatari Masahide
• Ikeda Kosuke

Classifications

• H05K1/0271 Primary

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

• H05K1/113

  Via provided in pad; Pad over filled via · CPC title

• H05K3/4673

  Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer (similar methods for protective coatings H05K3/28) · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H05K3/285 Primary

  Permanent coating compositions · CPC title