Fast and flexible ram reader and writer

Patent metadata

Field	Value
Publication number	US-2023376229-A1
Application number	US-202217663847-A
Country	US
Kind code	A1
Filing date	May 18, 2022
Priority date	May 18, 2022
Publication date	Nov 23, 2023
Grant date	—

Abstract

A circuit for reading or writing a RAM includes a shift register coupled to the RAM, a test data input, and a test data output. The circuit further includes a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.

First claim

What is claimed is:

1 . A circuit for reading or writing a random access memory (RAM), the circuit comprising:
a shift register coupled to the RAM, a test data input, and a test data output; and a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.

2 . The circuit of claim 1 , wherein the control circuit is configured to generate each pulse in accordance with a counter repeating every N clock cycles.

3 . The circuit of claim 2 , further coupled to a test controller running a finite state machine in accordance with an IEEE 1149.1 standard.

4 . The circuit of claim 3 , wherein the counter is configured to activate and count in accordance with the finite state machine.

5 . The circuit of claim 3 , further comprising an update register, wherein the RAM access operation includes a data transfer between the shift register and the update register and a data transfer between the update register and the RAM.

6 . The circuit of claim 3 , wherein the test data input is a serial test data input pin and the test data output is a serial test data output pin, and wherein the parallel factor is 1.

7 . The circuit of claim 3 , wherein the test data input includes a serial test data input pin and at least one parallel data loading pin, wherein the test data output includes a serial test data output pin and the at least one parallel data loading pin, each of the at least one parallel data loading pin coupled to a section of the shift register via a multiplexer (MUX), and wherein the parallel factor is a number of the at least one parallel data loading pin+1.

8 . The circuit of claim 1 , wherein the test data input includes at least one parallel data loading pin coupled to a peripheral device, and wherein the parallel factor is a number of the at least one parallel data loading pin.

9 . A method to write a random access memory (RAM), the method comprising:
loading, by a RAM access circuit coupled to the RAM, data from a test data input into a shift register of the RAM access circuit; and generating, by the RAM access circuit, a pulse every N clock cycles, each pulse triggering a RAM write operation transferring the data loaded into the shift register to the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in the test data input configured for parallel data loading.

10 . The method of claim 9 , wherein the RAM access circuit is configured to generate each pulse in accordance with a counter repeating every N clock cycles.

11 . The method of claim 10 , wherein the RAM access circuit is coupled to a test controller running a finite state machine in accordance with an IEEE 1149.1 standard.

12 . The method of claim 11 , wherein the counter is configured to activate and count in accordance with the finite state machine.

13 . The method of claim 11 , wherein the RAM access circuit includes an update register, and wherein the RAM write operation includes transferring the data from the shift register to the update register and subsequently transferring the data from the update register to the RAM.

14 . The method of claim 11 , wherein the test data input is a serial test data input pin, and wherein the parallel factor is 1.

15 . The method of claim 11 , wherein the test data input includes a serial test data input pin and at least one parallel data loading pin, each of the at least one parallel data loading pin coupled to a section of the shift register via a multiplexer (MUX), and wherein the parallel factor is a number of the at least one parallel data loading pin+1.

16 . The method of claim 9 , wherein the test data input includes at least one parallel data loading pin coupled to a peripheral device, and wherein the parallel factor is a number of the at least one parallel data loading pin.

17 . A method to read a random access memory (RAM), the method comprising:
generating, by a RAM access circuit coupled to the RAM and a test data output, a pulse every N clock cycles, each pulse triggering a RAM read operation loading data from the RAM into a shift register of the RAM access circuit, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in the test data output configured for parallel data loading; and transferring, by the RAM access circuit, the data loaded into the shift register to the test data output.

18 . The method of claim 17 , wherein the RAM access circuit includes an update register, and wherein the RAM read operation includes transferring the data from the RAM to the update register and subsequently transferring the data from the update register to the shift register.

19 . The method of claim 17 , wherein the test data output includes a serial test data output pin and at least one parallel data loading pin, each of the at least one parallel data loading pin coupled to a section of the shift register via a multiplexer (MUX), and wherein the parallel factor is a number of the at least one parallel data loading pin+1.

20 . The method of claim 17 , wherein the RAM access circuit is configured to generate each pulse in accordance with a counter repeating every N clock cycles.

21 . A device comprising:
a random access memory (RAM); a processor; and a RAM access circuit comprising:
a shift register coupled to the RAM, a test data input, and a test data output; and
a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.

Assignees

• St Microelectronics Srl

Inventors

• Girardi Walter

Classifications

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0602

  specifically adapted to achieve a particular effect · CPC title

• G06F3/0671

  In-line storage system · CPC title

• G11C29/48 Primary

  Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title