Display panel and display apparatus including the same

Patent metadata

Field	Value
Publication number	US-2023371332-A1
Application number	US-202318358009-A
Country	US
Kind code	A1
Filing date	Jul 24, 2023
Priority date	Sep 3, 2020
Publication date	Nov 16, 2023
Grant date	—

Abstract

A display panel includes: a substrate including a main display area, a first component area, a second component area, and a peripheral area; a first subpixel on the main display area, and a first pixel circuit connected to the first subpixel; a second subpixel on the first component area; a second pixel circuit spaced apart from the second subpixel; and a connection wiring connecting the second subpixel to the second pixel circuit.

First claim

What is claimed is:

1 . A display panel comprising:
a substrate comprising a main display area, a first component area, a second component area, and a peripheral area; a first subpixel on the main display area, and a first pixel circuit connected to the first subpixel; a second subpixel on the first component area; a second pixel circuit spaced apart from the second subpixel; a connection wiring connecting the second subpixel to the second pixel circuit; a main scan line extending in a first direction; and a scan connection line connected to the main scan line.

2 . The display panel of claim 1 , wherein the second pixel circuit is in the peripheral area.

3 . The display panel of claim 1 , wherein the connection wiring comprises a transparent conductive material.

4 . The display panel of claim 3 , further comprising an additional connection wiring connecting the connection wiring to the second pixel circuit, wherein the additional connection wiring comprises a material different from a material of the connection wiring.

5 . The display panel of claim 1 , wherein the first subpixel and the second subpixel are configured to emit a same color of light, and
a size of the second subpixel is greater than a size of the first subpixel.

6 . The display panel of claim 1 , wherein the second pixel circuit is between the first component area and the second component area.

7 . The display panel of claim 1 , further comprising a third subpixel between the first component area and the second component area.

8 . The display panel of claim 7 , wherein
the third subpixel is connected to a third pixel circuit in the peripheral area.

9 . The display panel of claim 1 , wherein the scan connection line surrounds one side of the first component area.

10 . The display panel of claim 1 , wherein the scan connection line is in the peripheral area.

11 . A display panel comprising:
a substrate comprising a main display area, a first component area, a second component area, and a peripheral area; a first subpixel on the main display area and a first pixel circuit connected to the first subpixel, the first subpixel comprising a first pixel electrode and a first emission layer; a second subpixel on the first component area, the second subpixel comprising a second pixel electrode and a second emission layer; a second pixel circuit spaced apart from the second subpixel; and a connection wiring connecting the second subpixel to the second pixel circuit, wherein the first pixel electrode or the second pixel electrode and the connection wiring are formed by a same process.

12 . The display panel of claim 11 , further comprising:
an opposite electrode on each of the first emission layer and the second emission layer; and an upper layer on the opposite electrode, wherein an end of the opposite electrode and an end of the upper layer coincide with each other.

13 . The display panel of claim 11 , wherein the second pixel circuit is in the peripheral area.

14 . The display panel of claim 11 , wherein the connection wiring comprises a transparent conductive material.

15 . The display panel of claim 14 , further comprising an additional connection wiring connecting the connection wiring to the second pixel circuit, wherein the additional connection wiring comprises a material different from a material of the connection wiring.

16 . The display panel of claim 11 , wherein the first subpixel and the second subpixel are configured to emit a same color of light, and
wherein a size of the second subpixel is greater than a size of the first subpixel.

17 . The display panel of claim 11 , wherein the second pixel circuit is between the first component area and the second component area.

18 . The display panel of claim 11 , further comprising a third subpixel between the first component area and the second component area.

19 . The display panel of claim 18 , wherein
the third subpixel is connected to a third pixel circuit in the peripheral area.

20 . The display panel of claim 11 , further comprising a bottom metal layer on the first component area.

21 . The display panel of claim 20 , further comprising a dummy subpixel in the peripheral area or the first component area and the second component area.

22 . The display panel of claim 11 , wherein the substrate further comprises a third component area.

23 . A display panel comprising:
a substrate comprising a main display area, a first component area, a second component area, and a peripheral area; a first subpixel on the main display area and a first pixel circuit connected to the first subpixel; a second subpixel on the first component area; a second pixel circuit spaced apart from the second subpixel; and a connection wiring connecting the second subpixel to the second pixel circuit, wherein no subpixels are located in the second component area.

24 . The display panel of claim 23 , wherein each of the first component area and the second component area includes a transmission area,
wherein a size of the transmission area of the second component area is greater than a size of the transmission area of the first component area.

25 . The display panel of claim 24 , wherein a light transmittance of the second component area is greater than a light transmittance of the first component area.

26 . A display panel comprising:
a substrate comprising a main display area, a first component area, a second component area, and a peripheral area; a first subpixel on the main display area and a first pixel circuit connected to the first subpixel; a second subpixel on the first component area; a second pixel circuit spaced apart from the second subpixel; a first connection wiring connecting the second subpixel to the second pixel circuit; a third subpixel on the second component area; a third pixel circuit spaced apart from the third subpixel; and a second connection wiring connecting the third subpixel to the third pixel circuit.

27 . The display panel of claim 26 , wherein the second pixel circuit and the third pixel circuit are in the peripheral area.

28 . The display panel of claim 26 , wherein the first connection wiring and the second connecting wiring comprise a transparent conductive material.

29 . The display panel of claim 26 , wherein the second pixel circuit or the third pixel circuit is between the first component area and the second component area.

30 . The display panel of claim 1 , further comprising a fourth subpixel between the first component area and the second component area.

Assignees

• Samsung Display Co Ltd

Inventors

• BOK Seunglyong
• Park Okkyung
• Son Youngran

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• H10K59/122 Primary

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K59/121

  characterised by the geometry or disposition of pixel elements · CPC title

• H10K50/84

  Passivation; Containers; Encapsulations · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title