Device, method and system to supplement a cache with a randomized victim cache

Patent metadata

Field	Value
Publication number	US-2023350814-A1
Application number	US-202218078762-A
Country	US
Kind code	A1
Filing date	Dec 9, 2022
Priority date	Apr 27, 2022
Publication date	Nov 2, 2023
Grant date	—

Abstract

Techniques and mechanisms for a victim cache to operate in conjunction with another cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a primary cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the primary cache. The victim cache is accessed using an independently randomized mapping. Subsequently, a request to access the first line results in a search of the victim cache and the primary cache. Based on the search, the first line is evicted from the victim cache, and reinserted in the primary cache. In another embodiment, reinsertion of the first line in the primary cache includes the first line and a third line being swapped between the primary cache and the victim cache.

First claim

What is claimed is:

1 . An integrated circuit comprising:
first circuitry to:
receive a first message which indicates a first address which corresponds to a first line of data; and
identify a first location of a preliminary cache based on the message;
second circuitry coupled to the first circuitry, wherein, based on the first message, the second circuitry is to:
identify a second location of a victim cache, comprising the second circuitry to perform a calculation based on one of an encryption key or a hash function;
move a second line from the first location to the second location; and
store the first line to the first location.

2 . The integrated circuit of claim 1 , wherein the second circuitry to identify the second location comprises the second circuitry to determine, based on the calculation, an index of a set of the victim cache.

3 . The integrated circuit of claim 1 , wherein the primary cache comprises a skewed cache.

4 . The integrated circuit of claim 1 , wherein the first circuitry is further to receive a second message which indicates a second address which corresponds to the second line; and
wherein the second circuitry is further to move the second line from the second location to the preliminary cache based on the second message.

5 . The integrated circuit of claim 4 , wherein the second circuitry to move the second line from the second location to the preliminary cache comprises the second circuitry to swap the second line and a third line between the preliminary cache and the victim cache.

6 . The integrated circuit of claim 5 , wherein the second line and the third line are swapped based on a valid state of the third line.

7 . The integrated circuit of claim 4 , wherein, based on the first message, the second circuitry is further to evict a third line from the second location to a memory before the second circuitry is to move the second line from the first location to the second location.

8 . The integrated circuit of claim 7 , wherein the second circuitry is to evict the third line based on a valid state of the third line.

9 . The integrated circuit of claim 4 , wherein the second circuitry is to move the second line to the second location based on a valid state of the second line.

10 . A method at a processor, the method comprising:
receiving a first message which indicates a first address which corresponds to a first line of data; identifying a first location of a preliminary cache based on the message; based on the first message:
identifying a second location of a victim cache, comprising performing a calculation based on one of an encryption key or a hash function;
moving a second line from the first location to the second location; and
storing the first line to the first location.

11 . The method of claim 10 , wherein identifying the second location comprises determining, based on the calculation, an index of a set of the victim cache.

12 . The method of claim 10 , wherein the primary cache comprises a skewed cache.

13 . The method of claim 10 , further comprising:
receiving a second message which indicates a second address which corresponds to the second line; and moving the second line from the second location to the preliminary cache based on the second message.

14 . The method of claim 13 , wherein moving the second line from the second location to the preliminary cache comprises swapping the second line and a third line between the preliminary cache and the victim cache.

15 . The method of claim 13 , further comprising:
based on the first message, evicting a third line from the second location to a memory before the second line is moved from the first location to the second location.

16 . A system comprising:
an integrated circuit (IC) chip comprising:
first circuitry to:
receive a first message which indicates a first address which corresponds to a first line of data; and
identify a first location of a preliminary cache based on the message;

second circuitry coupled to the first circuitry, wherein, based on the first message, the second circuitry is to:
identify a second location of a victim cache, comprising the second circuitry to perform a calculation based on one of an encryption key or a hash function;
move a second line from the first location to the second location; and
store the first line to the first location; and

a display device coupled to the IC chip, the display device to display an image based on a signal communicated with the IC chip.

17 . The system of claim 16 , wherein the second circuitry to identify the second location comprises the second circuitry to determine, based on the calculation, an index of a set of the victim cache.

18 . The system of claim 16 , wherein the primary cache comprises a skewed cache.

19 . The system of claim 16 , wherein the first circuitry is further to receive a second message which indicates a second address which corresponds to the second line; and
wherein the second circuitry is further to move the second line from the second location to the preliminary cache based on the second message.

20 . The system of claim 19 , wherein the second circuitry to move the second line from the second location to the preliminary cache comprises the second circuitry to swap the second line and a third line between the preliminary cache and the victim cache.

Assignees

• Intel Corp

Inventors

• Unterluggauer Thomas
• Liu Fangfei
• Rozas Carlos
• Constable Scott
• Pokam Gilles
• Mckeen Francis
• Wilkerson Christopher
• Hallnor Erik

Classifications

• G06F12/1408 Primary

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/121

  using replacement algorithms · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title