High electron mobility transistor and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2023335614-A1
Application number	US-202318215787-A
Country	US
Kind code	A1
Filing date	Jun 28, 2023
Priority date	Oct 1, 2019
Publication date	Oct 19, 2023
Grant date	—

Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

First claim

What is claimed is:

1 . A method for fabricating high electron mobility transistor (HEMT), comprising:
forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; forming a second hard mask on the first hard mask; patterning the second hard mask, the first hard mask, the second barrier layer, the first barrier layer, and the buffer layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

2 . The method of claim 1 , further comprising:
forming a third hard mask on the second hard mask; removing the third hard mask, the second hard mask, the first hard mask, and the second barrier layer to form the recess; forming the p-type semiconductor layer in the recess; removing the third hard mask and the second hard mask; forming a passivation layer on the first hard mask; forming a gate electrode on the p-type semiconductor layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

3 . The method of claim 2 , wherein the second hard mask and the third hard mask comprise same material.

4 . The method of claim 1 , wherein the first hard mask and the second hard mask comprise different materials.

5 . The method of claim 1 , wherein the first barrier layer and the second barrier layer comprise Al x Ga 1-x N.

6 . The method of claim 5 , wherein the first barrier layer and the second barrier layer comprise different concentrations of Al.

7 . The method of claim 5 , wherein a concentration of Al of the first barrier layer is less than a concentration of Al of the second barrier layer.

8 . The method of claim 1 , wherein a thickness of the first barrier layer is less than a thickness of the second barrier layer.

9 . The method of claim 1 , further comprising forming a metal nitride layer on the buffer layer before forming the first barrier layer.

10 . The method of claim 1 , wherein the p-type semiconductor layer comprises p-type gallium nitride (pGaN).

Assignees

• United Microelectronics Corp

Inventors

• Chang Chun-Ming
• Huang Che-Hung
• Liao Wen-Jung
• Hou Chun-Liang
• Yeh Chih-Tung

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/4755

  having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title