Laminated ceramic capacitor and method for manufacturing laminated ceramic capacitor
US-2015155098-A1 · Jun 4, 2015 · US
Manufacturing method of multilayer ceramic electronic device
US2023326680A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2023326680-A1 |
| Application number | US-202318327805-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 1, 2023 |
| Priority date | Oct 30, 2020 |
| Publication date | Oct 12, 2023 |
| Grant date | — |
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- Title
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Abstract
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A manufacturing method of a multilayer ceramic electronic device includes: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is formed from the each of internal electrode patterns and each dielectric layer is formed from the each of the dielectric green sheets wherein, in the each internal electrode layer, an Au concentration near each interface between the each internal electrode layer and the each dielectric layer is larger than an Au concentration in each center portion in a thickness direction.
First claim
Opening claim text (preview).
1 . A manufacturing method of a multilayer ceramic electronic device, comprising: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is formed from the each of internal electrode patterns and each dielectric layer is formed from the each of the dielectric green sheets wherein, in the each internal electrode layer, an Au concentration near each interface between the each internal electrode layer and the each dielectric layer is larger than an Au concentration in each center portion in a thickness direction. 2 . The manufacturing method as claimed in claim 1 , wherein, in the forming of the each of stack units, the each of internal electrode patterns is formed on the each of dielectric green sheet by a vacuum deposition process. 3 . The manufacturing method as claimed in claim 1 , wherein a total content of Sn and Au relative to Ni in the each internal electrode layer is 0.01 at % or more and 95 at % or less. 4 . The manufacturing method as claimed in claim 1 , wherein a total content of Sn and Au relative to Ni in the each internal electrode layer is 0.2 at % or more and 10 at % or less. 5 . The manufacturing method as claimed in claim 1 , wherein a content of Au is smaller than a content of Sn in the each internal electrode layer. 6 . The manufacturing method as claimed in claim 1 , wherein, in the each internal electrode layer, a Sn concentration near the each interface is larger than a Sn concentration in the each center portion.
Assignees
Inventors
Classifications
- H01G4/30Primary
Stacked capacitors (H01G4/33 takes precedence) · CPC title
- H01G4/008Primary
Selection of materials · CPC title
based on titanium oxides or titanates (H01G4/1245 takes precedence) · CPC title
- C04B35/4682Primary
based on BaTiO3 perovskite phase · CPC title
Form of non-self-supporting electrodes · CPC title
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- What does patent US2023326680A1 cover?
- A manufacturing method of a multilayer ceramic electronic device includes: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is …
- Who is the assignee on this patent?
- Taiyo Yuden Kk
- What technology area does this patent fall under?
- Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Oct 12 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).