Diagnostic System and Method for Network Synchronized Time in Safety Applications

US2023318728A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023318728-A1
Application numberUS-202217709341-A
CountryUS
Kind codeA1
Filing dateMar 30, 2022
Priority dateMar 30, 2022
Publication dateOct 5, 2023
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

To improve integrity of time synchronization, a node in a safety rated system verifies that its clock remains synchronized to another clock. Two adjacent, time-synchronized nodes transmit diagnostic messages to each other at an agreed upon interval and generate timestamps when the diagnostic message is received from the other node. The nodes then transmit their respective timestamp back to the sending node. Clock drift is detected by comparing a difference between the two timestamps at which the messages were received against a threshold. To avoid accidental detection of clock drift, a difference in transmission delays between the two nodes is stored in a FIFO buffer. Each node monitors the average of the data in the FIFO buffer. If the average deviates from the target value by too great a value, then the node determines the values of the clocks have skewed beyond an acceptable range and generates a fault condition.

First claim

Opening claim text (preview).

We claim: 1 . A method of monitoring clock circuits for use in a safety rated application, the method comprising the steps of: synchronizing a first clock in a first node with a second clock in a second node; transmitting a first diagnostic message from the first node to the second node at a first time based on the first clock; transmitting a second diagnostic message from the second node to the first node at the first time based on the second clock; generating a first diagnostic timestamp in the first node corresponding to receipt of the second diagnostic message; generating a second diagnostic timestamp in the second node corresponding to receipt of the first diagnostic message; transmitting the first diagnostic timestamp from the first node to the second node; transmitting the second diagnostic timestamp from the second node to the first node; storing a diagnostic value in a buffer for either the first node or the second node, wherein the diagnostic value is determined as a function of the first diagnostic timestamp and the second diagnostic timestamp; and determining a clock skew between the first clock and the second clock as a function of the diagnostic value in either the first node or the second node. 2 . The method of claim 1 , wherein the diagnostic value is a difference between the first diagnostic timestamp and the second diagnostic timestamp. 3 . The method of claim 1 , further comprising the steps of: determining a first transmission time for the first diagnostic message from the first node to the second node as a difference between the first time and the second diagnostic timestamp; and determining a second transmission time for the second diagnostic message from the second node to the first node as a difference between the first time and the first diagnostic timestamp, wherein the diagnostic value is a difference between the first transmission time and the second transmission time. 4 . The method of claim 1 , further comprising the step of determining an offset time value between the first clock and the second clock as a function of the first time, the first diagnostic timestamp, and the second diagnostic timestamp, wherein the diagnostic value is the offset time value. 5 . The method of claim 1 , wherein the step of determining the clock skew further comprises the steps of: storing a plurality of values for the diagnostic value in the buffer in a first-in, first-out configuration; and determining a mean value of the plurality of values in the buffer. 6 . The method of claim 5 , further comprising the step of determining a standard deviation of the plurality of values in the buffer, wherein the clock skew between the first clock and the second clock is determined as a function of the mean value and the standard deviation. 7 . The method of claim 5 , wherein the step of determining the clock skew further comprises the steps of: determining a difference between the mean value and a target mean value; and maintaining a cumulative summation of the difference between the mean value and a target mean value when the difference exceeds a predefined threshold. 8 . The method of claim 7 , wherein the step of determining the clock skew further comprises the steps of: determining a clock skew in a first polarity when the cumulative summation exceeds a second predefined threshold, determining a slope of the mean value with respect to time, and determining a clock skew in a second polarity, opposite the first polarity, when the slope of the mean value exceeds a third predefined threshold. 9 . The method of claim 7 , wherein: the step of maintaining the cumulative summation of the difference between the mean value and the target mean value when the difference exceeds the predefined threshold further comprises the steps of: maintaining a first cumulative summation when the difference exceeds a first predefined threshold, and maintaining a second cumulative summation when the difference exceeds a second predefined threshold; and the step of determining the clock skew further comprises the steps of: determining the clock skew in a first polarity when the first cumulative summation exceeds a third predefined threshold, and determining the clock skew in a second polarity, opposite the first polarity, when the second cumulative summation exceeds a fourth predefined threshold. 10 . A node in an industrial control system configured to generate a clock signal for use in a safety rated application, the node comprising: a communication port configured to connect to an industrial network for communication with at least one additional node on the industrial network; a clock circuit generating a first clock signal; and a processor configured to: synchronize the first clock signal with a second clock signal in the at least one additional node; transmit a first diagnostic message to the at least one additional node at a first time based on the first clock signal; receive a second diagnostic message from the at least one additional node, wherein the second diagnostic message is transferred from the at least one additional node at the first time based on the second clock signal; generate a first diagnostic timestamp as a function of the first clock signal corresponding to receipt of the second diagnostic message; receive a second diagnostic timestamp from the at least one additional node, wherein the second diagnostic timestamp corresponds to a time at which the at least one additional node received the first diagnostic message; store a diagnostic value in a buffer, wherein the diagnostic value is determined as a function of the first diagnostic timestamp and the second diagnostic timestamp; and determine a clock skew between the first clock signal and the second clock signal as a function of the diagnostic value. 11 . The node of claim 10 , wherein the diagnostic value is a difference between the first diagnostic timestamp and the second diagnostic timestamp. 12 . The node of claim 10 , wherein the processor is further configured to: determine a first transmission time for the first diagnostic message from the first node to the second node as a difference between the first time and the second diagnostic timestamp; and determine a second transmission time for the second diagnostic message from the second node to the first node as a difference between the first time and the first diagnostic timestamp, wherein the diagnostic value is a difference between the first transmission time and the second transmission time. 13 . The node of claim 10 wherein the processor is further configured to determine an offset time value between the first clock signal and the second clock signal as a function of the first time, the first diagnostic timestamp, and the second diagnostic timestamp, wherein the diagnostic value is the offset time value. 14 . The node of claim 10 , wherein the processor is further configured to determine the clock skew by: storing a plurality of values for the diagnostic value in the buffer in a first-in, first-out configuration; and determining a mean value of the plurality of values in the buffer. 15 . The node of claim 14 , wherein the processor is further configured to determine the clock skew by: determining a standard deviation of the plurality of values in the buffer, and determining the clock skew as a function of the mean value and the standard deviation. 16 . The node of claim 14 , wherein the processor is further configured to determine the clock skew by: determining a difference between the mean value

Assignees

Inventors

Classifications

  • H04J3/0661Primary

    using timestamps · CPC title

  • Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers (pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06) · CPC title

  • H04J3/0667Primary

    Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title

  • electric · CPC title

  • Bus networks · CPC title

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What does patent US2023318728A1 cover?
To improve integrity of time synchronization, a node in a safety rated system verifies that its clock remains synchronized to another clock. Two adjacent, time-synchronized nodes transmit diagnostic messages to each other at an agreed upon interval and generate timestamps when the diagnostic message is received from the other node. The nodes then transmit their respective timestamp back to the …
Who is the assignee on this patent?
Rockwell Automation Tech Inc
What technology area does this patent fall under?
Primary CPC classification H04J3/0661. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 05 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).