Device and method for operating the same

Patent metadata

Field	Value
Publication number	US-2023299576-A1
Application number	US-202318323368-A
Country	US
Kind code	A1
Filing date	May 24, 2023
Priority date	Jul 22, 2020
Publication date	Sep 21, 2023
Grant date	—

Abstract

A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

First claim

What is claimed is:

1 . A device, comprising:
a bias generator comprising a first transistor; an electrostatic discharge (ESD) driver comprising a second transistor and a third transistor coupled to each other in series; and a logic circuit configured to generate a logic control signal, wherein when the first transistor is turned on by a detection signal, the first transistor is turned off.

2 . The device of claim 1 , wherein a first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

3 . The device of claim 2 , wherein a first terminal of the second transistor is configured to receive an input signal, a second terminal of the second transistor is coupled to a first terminal of the third transistor, and a second terminal of the third transistor is configured to receive the reference voltage signal.

4 . The device of claim 3 , wherein the second transistor is controlled according to the logic control signal, and the third transistor is controlled according to the reference voltage signal, wherein a first voltage across the second transistor and a second voltage across the third transistor are substantially the same.

5 . The device of claim 4 , wherein the first transistor is configured to transmit, in response to the detection signal, the reference voltage signal as a bias signal, wherein the third transistor is controlled according to the bias signal.

6 . The device of claim 3 , wherein the input signal is applied to the second transistor and the third transistor equally.

7 . The device of claim 2 , further comprising:
a transmission gate configured to provide the logic control signal to the second transistor, wherein the transmission gate stops providing the logic control_signal to the second transistor in response to the ESD event being detected.

8 . The device of claim 7 , further comprising:
a secondary bias generator configured to provide a secondary bias signal to the second transistor in response to the ESD event being detected so that a first voltage across the second transistor and a second voltage across the third transistor are substantially the same.

9 . A device, comprising:
an ESD detector coupled to a pad, configured to detect an input signal at the pad, and configured to generate a detection signal in response to an ESD event being detected; a bias generator coupled to the ESD detector and configured to transmit a reference voltage signal according to the detection signal; an ESD driver configured to receive the reference voltage signal and comprising:
a first transistor; and
a second transistor coupled to the first transistor; and
a transmission gate coupled to the first transistor, wherein when the ESD event occurs, the transmission gate is turned off so that a first voltage drop across the first transistor and a second voltage drop across the second transistor are substantially the same.

10 . The device of claim 9 , wherein the ESD detector comprises:
at least two diodes coupled to each other at an input terminal, wherein the input terminal is configured to receive the input signal; and a RC circuit coupled to the at least two diodes in parallel.

11 . The device of claim 10 , wherein the at least two diodes comprise:
a first diode coupled to a ground terminal; and a second diode configured to receive the reference voltage signal.

12 . The device of claim 11 , wherein the RC circuit comprises:
a resistor; and a capacitor coupled to the resistor at an output terminal, wherein the output terminal is configured to generate the detection signal when the ESD event occurs.

13 . The device of claim 12 , wherein the resistor is configured to receive the reference voltage signal, and the capacitor is coupled to the ground terminal.

14 . The device of claim 12 , wherein the capacitor is configured to receive the reference voltage signal, and the resistor is coupled to the ground terminal.

15 . A method, comprising:
outputting, by a logic gate, a logic control signal; transmitting, by a bias generator, a reference voltage signal as a bias signal according to a detection signal in response to an ESD event being detected; and controlling a first transistor of an ESD driver and a second transistor of the ESD driver according to the logic control signal and the bias signal, wherein when the ESD event occurs, the bias generator is turned on to pull a voltage at a control terminal of the second transistor.

16 . The method of claim 15 , wherein the voltage at the control terminal of the second transistor is pulled to a ground voltage or a power supply voltage.

17 . The method of claim 15 , wherein a first terminal of the first transistor is configured to receive an input signal, a second terminal of the first transistor is coupled to a first terminal of the second transistor, and a second terminal of the second transistor is configured to receive the reference voltage signal.

18 . The method of claim 17 , wherein the input signal is applied to the first transistor and the second transistor equally.

19 . The method of claim 15 , further comprising:
providing the logic control signal to the first transistor; and stopping providing the logic control signal to the first transistor in response to the ESD event being detected.

20 . The method of claim 19 , further comprising:
providing a secondary bias signal to the first transistor in response to the ESD event being detected so that a first voltage across the first transistor and a second voltage across the second transistor are substantially the same.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Po-Lin
• Su Yu-Ti
• Hsu Chia-Wei
• Tsai Ming-Fu
• Su shu-yu
• Chu Li-Wei
• Lee Jam-Wem
• Chang Chia-Jung
• Cheng Hsiang-Hui

Classifications

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D89/819 Primary

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H10D89/60 Primary

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title