Substrate for manufacturing display device, and method for manufacturing display device by using same

Patent metadata

Field	Value
Publication number	US-2023299055-A1
Application number	US-202018020608-A
Country	US
Kind code	A1
Filing date	Aug 10, 2020
Priority date	Aug 10, 2020
Publication date	Sep 21, 2023
Grant date	—

Abstract

A method for manufacturing a substrate for manufacturing a display device, according to the present invention, comprises the steps of: (a) forming, at predetermined intervals, assembly electrodes extending in one direction on a base part, and forming a dielectric layer so as to cover the assembly electrodes; (b) forming, on the dielectric layer, metal patterns so as to overlap the assembly electrodes; (c) forming partition parts on the dielectric layer so as to cover the metal patterns, and then forming assembly holes so as to overlap the metal patterns; and (d) removing the metal patterns exposed through the assembly holes, wherein, in step (d), a groove part is formed on the surface of each partition part, which forms the inner surface of each assembly hole, as the metal patterns are removed.

First claim

1 . A substrate for manufacturing a display device, the substrate comprising:
a base; assembly electrodes extending in one direction and disposed at predetermined gaps on one surface of the base; a dielectric layer disposed on the base to cover the assembly electrodes; and a barrier rib stacked on the dielectric layer while forming assembly holes, in which semiconductor light-emitting elements are seated, to overlap the assembly electrodes, wherein the barrier rib includes grooves formed in a surface defining inner surfaces of the assembly holes.

2 . The substrate of claim 1 , wherein each of the grooves is formed in a bottom surface of the assembly hole.

3 . The substrate of claim 2 , wherein the groove is formed with a predetermined width along a circumference of the assembly hole.

4 . The substrate of claim 1 , wherein each of the grooves is formed to have a thickness of 20 nm to 200 nm from a bottom surface of the assembly hole.

5 . The substrate of claim 1 , wherein the barrier rib is formed of SiO 2 or SiN x .

6 . A method for manufacturing a substrate for manufacturing a display device, the method comprising:
(a) forming assembly electrodes extending in one direction on a base at predetermined distances, and forming a dielectric layer to cover the assembly electrodes; (b) forming metal patterns on the dielectric layer to overlap the assembly electrodes; (c) forming a barrier rib on the dielectric layer to cover the metal patterns, and then forming assembly holes to overlap the metal patterns; and (d) removing the metal patterns exposed through the assembly holes, wherein in the step (d), the metal patterns are removed such that the grooves are formed in a surface of the barrier rib defining inner surfaces of the assembly holes.

7 . The method of claim 6 , wherein each of the metal pattern shares a center with the assembly hole, and
wherein the metal pattern is formed to have an area wider than that of the assembly hole.

8 . The method of claim 7 , wherein each of the grooves is formed with a predetermined width along a circumference of the assembly hole.

9 . The method of claim 6 , wherein in the step (b), each of the metal patterns is formed with a thickness of 20 nm to 200 nm on the dielectric layer.

10 . The method of claim 6 , wherein the barrier rib is formed of SiO 2 or SiN x , and
wherein in the step (c), the barrier rib is etched using a CF x -based etching gas to form the assembly holes.

11 . The method of claim 10 , wherein the metal pattern is formed of a metal material having an etching selectivity of 10:1 or more with the barrier rib for the CF x -based etching gas.

12 . The method of claim 6 , wherein in step (d), the metal pattern is removed through dry etching using a Cl 2 -based etching gas or wet etching.

Assignees

• Lg Electronics Inc

Inventors

• Park Changseo
• Lee Jinhyung
• Heo Younho
• Shin Yongil
• Kim Kisu

Classifications

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title