Fail-open isolator

US2023268270A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023268270-A1
Application numberUS-202217677729-A
CountryUS
Kind codeA1
Filing dateFeb 22, 2022
Priority dateFeb 22, 2022
Publication dateAug 24, 2023
Grant date

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns “on” the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

First claim

Opening claim text (preview).

What is claimed is: 1 . An integrated circuit (IC), comprising: a first IC terminal; a second IC terminal; a fuse having a first fuse terminal and a second fuse terminal, the first fuse terminal coupled to the first IC terminal and the second fuse terminal configured to have a first voltage; a first transistor having a control input and first and second current terminals, the first current terminal coupled to the second fuse terminal, and the second current terminal coupled to the second IC terminal; a comparator having a comparator output, the comparator configured to compare a reference voltage to a second voltage based on the first voltage and to assert a comparator output signal to a first logic state responsive to the second voltage exceeding the reference voltage; and a logic circuit having a first logic circuit input and a first logic circuit output, the comparator output coupled to the first logic circuit input, and the logic circuit is configured to assert a first control signal on the first logic circuit output to turn on the first transistor responsive to the comparator asserting the comparator output signal to the first logic state. 2 . The IC of claim 1 , in which the fuse is configured to have a trip current level, and responsive to a current through the fuse exceeding the trip current level, the logic circuit is configured to turn on the first transistor in a saturation region, and current through the fuse causes the fuse to blow. 3 . The IC of claim 2 , in which responsive to the current through the fuse being below the trip current level, the logic circuit is configured to turn on the first transistor into a linear region and a voltage difference between the first transistor's first and second current terminals reducing the first voltage. 4 . The IC of claim 1 , in which the logic circuit has a second control output, and the IC further includes: a second transistor having a second control input and third and fourth current terminals, the third current terminal coupled to the second fuse terminal, and the second control input coupled to the second control output; a capacitor coupled between the fourth current terminal and the second IC terminal; and a voltage divider coupled in parallel with the capacitor, the voltage divider configured to provide the second voltage. 5 . The IC of claim 4 , in which, in which, responsive to the comparator asserting the comparator output signal to the first logic state, the logic circuit is configured to assert a second control signal on the second logic circuit output to turn off the second transistor. 6 . The IC of claim 5 , in which the logic circuit includes at least one delay buffer which causes the logic circuit to turn off the second transistor before turning on the first transistor. 7 . The IC of claim 1 , in which the first and second IC terminals are power supply terminals. 8 . The IC of claim 1 , in which the fuse has a serpentine conductive element between the first and second fuse terminals. 9 . The IC of claim 8 , in which the serpentine conductive element has generally parallel first, second, and third conductive elements, the first conductive element disposed between the second and third conductive element, and, in response to current flowing through the first, second, and third conductive element, heat generated by the first and third conductive elements elevates the temperature of the first conductive element. 10 . The IC of claim 1 , in which the comparator is a first comparator, and the IC further includes: a second transistor having a second transistor control input; a temperature sensor; a second comparator configured to assert a second comparator output signal to the first logic state in response to a temperature signal from the temperature sensor being greater than a second threshold voltage; a transistor turn-off circuit configured to generate a voltage on the second transistor control input to turn off the second transistor responsive to the second comparator output signal being in the first logic state. 11 . A device, comprising: a first device terminal; a second device terminal; a fuse having a first fuse terminal and a second fuse terminal, the first fuse terminal coupled to the first device terminal and the second fuse terminal configured to have a first voltage; a first transistor having a first control input and first and second current terminals, the first current terminal coupled to the second fuse terminal and the second current terminal coupled to the second device terminal; and a control circuit coupled to the first transistor and configured to: control the first transistor to operate in a saturation region in response to the first voltage exceeding a threshold and a current through the fuse exceeding a trip threshold current of the fuse; and control the first transistor to operate in a linear region in response to the first voltage exceeding a threshold and a current through the fuse being below the trip threshold current of the fuse. 12 . The device of claim 11 , further including a second transistor having a second control input and third and fourth current terminals, the third current terminal coupled to the second fuse terminal, and the logic circuit includes: first and second control outputs, the first control output coupled to the first control input, and the second control output coupled to the second control input; a capacitor coupled between the fourth current terminal and the second IC terminal; and a voltage divider coupled in parallel with the capacitor. 13 . The device of claim 12 , in which: the voltage divider is configured to produce a second voltage derived from the first voltage; and the logic circuit includes a comparator configured to compare the threshold to the second voltage. 14 . The device of claim 13 , in which the logic circuit is configured to cause the first transistor to be turned on and the second transistor to be turned off responsive to the comparator determining that second voltage exceeds the threshold. 15 . The device of claim 14 , in which the logic circuit includes at least one delay buffer which causes the logic circuit to turn off the second transistor before turning on the first transistor. 16 . The device of claim 11 , in which the first and second IC terminals are at least one of power supply terminals or input/output terminals. 17 . The device of claim 11 , in which the fuse is a self-heating fuse having a serpentine conductive element between the first and second fuse terminals. 18 . The device of claim 11 , in which the device is an isolator device having first and second sides separated by an isolation barrier, and the fuse, first circuit, first transistor, and control circuit are provided in at least one of the sides of the isolator device. 19 . A fuse, comprising: a first fuse terminal; a second fuse terminal; a serpentine conductive element coupled between the first and second fuse terminals, the serpentine conductive element including generally parallel first, second, and third conductive elements, the first conductive element disposed between the second and third conductive element. 20 . The fuse of claim 19 , in which: the first conductive element has a first width; the second conductive element has a second width; and the third conductive element has a third width, in which the first width is smaller than the both of the second and third widths.

Assignees

Inventors

Classifications

  • H10W20/493Primary

    Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

  • responsive to excess current (responsive to abnormal temperature caused by excess current H02H5/04) · CPC title

  • responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T) · CPC title

  • responsive to excess current {(current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025)} · CPC title

  • using a thermocouple · CPC title

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Frequently asked questions

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What does patent US2023268270A1 cover?
A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal coupl…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/493. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 24 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).