Degradation-aware training scheme for reliable memristor deep learning accelerator design

Patent metadata

Field	Value
Publication number	US-2023267997-A1
Application number	US-202318173242-A
Country	US
Kind code	A1
Filing date	Feb 23, 2023
Priority date	Feb 23, 2022
Publication date	Aug 24, 2023
Grant date	—

Abstract

A method, a system, and computer program product for degradation-aware training of neural networks are provided. A degradation of degraded memory cells of a memory array is detected, during a training of a neural network. A first set of writing parameter values to be applied to the one or more degraded memory cells and a second set of writing parameter values to be applied to the undegraded memory cells is determined using a model of the memory array tuned to account for the degradation of one or more memory cells. A writing operation is executed, by applying the first set of writing parameter values to the one or more degraded memory cells to compensate for the degradation of the one or more degraded memory cells and by applying the second set of writing parameter values to the undegraded memory cell.

First claim

What is claimed is:

1 . A method comprising:
detecting, during a training of a neural network, a degradation of one or more degraded memory cells of a memory array comprising a plurality of memory cells, at least a portion of the plurality of memory cells comprising an undegraded memory cell; determining, using a model of the memory array tuned to account for the degradation of one or more memory cells, a first set of writing parameter values to be applied to the one or more degraded memory cells and a second set of writing parameter values to be applied to the undegraded memory cells; and executing a writing operation, by applying the first set of writing parameter values to the one or more degraded memory cells to compensate for the degradation of the one or more degraded memory cells and by applying the second set of writing parameter values to the undegraded memory cell.

2 . The method of claim 1 , wherein the plurality of memory cells comprise resistive memory cells.

3 . The method of claim 1 , wherein detecting the degradation of one or more degraded memory cells comprises:
determining, using a degradation model, storing conductance values that are different from written conductance values.

4 . The method of claim 3 , wherein the degradation model processes the plurality of memory cells using as input a value of maximum resistance and the written conductance values to generate a matrix of the storing conductance values.

5 . The method of claim 1 , wherein detecting the degradation of one or more degraded memory cells comprises:
scanning, using a current meter, a conductance value of each memory cell of the plurality of memory cells; and determining a conductance change by comparing the conductance value of each memory cell to a previous conductance value stored by a buffer.

6 . The method of claim 1 , wherein the first set of writing parameter values and the second set of writing parameter values comprise a current, a voltage, a signal frequency or a pulse width.

7 . The method of claim 1 , wherein executing the writing operation, by applying the first set of writing parameter values to the one or more degraded memory cells to compensate for the degradation of the one or more degraded memory cells comprises reducing memory updates comprising a value of a writing amount, or a magnitude of change, or a frequency of change to the one or more degraded memory cells.

8 . The method of claim 7 , wherein the memory updates correspond to parameter updates during a training scheme for neural networks.

9 . A non-transitory storage medium comprising programming code, which when executed by at least one data processor, causes operations comprising:
detecting, during a training of a neural network, a degradation of one or more degraded memory cells of a memory array comprising a plurality of memory cells, at least a portion of the plurality of memory cells comprising an undegraded memory cell; determining, using a model of the memory array tuned to account for the degradation of one or more memory cells, a first set of writing parameter values to be applied to the one or more degraded memory cells and a second set of writing parameter values to be applied to the undegraded memory cells; and executing a writing operation, by applying the first set of writing parameter values to the one or more degraded memory cells to compensate for the degradation of the one or more degraded memory cells and by applying the second set of writing parameter values to the undegraded memory cell.

10 . The non-transitory computer-readable storage medium of claim 9 , wherein the plurality of memory cells comprise resistive memory cells.

11 . The non-transitory computer-readable storage medium of claim 9 , wherein detecting the degradation of one or more degraded memory cells comprises:
determining, using a degradation model, storing conductance values that are different from written conductance values, wherein the degradation model processes the plurality of memory cells using as input a value of maximum resistance and the written conductance values to generate a matrix of the storing conductance values.

12 . The non-transitory computer-readable storage medium of claim 9 , wherein detecting the degradation of one or more degraded memory cells comprises:
scanning, using a current meter, a conductance value of each memory cell of the plurality of memory cells; and determining a conductance change by comparing the conductance value of each memory cell to a previous conductance value stored by a buffer.

13 . The non-transitory computer-readable storage medium of claim 9 , wherein the first set of writing parameter values and the second set of writing parameter values comprise a current, a voltage, a signal frequency or a pulse width.

14 . The non-transitory computer-readable storage medium of claim 9 , wherein executing the writing operation, by applying the first set of writing parameter values to the one or more degraded memory cells to compensate for the degradation of the one or more degraded memory cells comprises reducing memory updates comprising a value of a writing amount, or a magnitude of change, or a frequency of change to the one or more degraded memory cells, wherein the memory updates correspond to parameter updates during a training scheme for neural networks.

15 . A system comprising:
at least one data processor; and at least one memory storing instructions, which when executed by the at least one data processor, cause operations comprising:
detecting, during a training of a neural network, a degradation of one or more degraded memory cells of a memory array comprising a plurality of memory cells, at least a portion of the plurality of memory cells comprising an undegraded memory cell;
determining, using a model of the memory array tuned to account for the degradation of one or more memory cells, a first set of writing parameter values to be applied to the one or more degraded memory cells and a second set of writing parameter values to be applied to the undegraded memory cells; and
executing a writing operation, by applying the first set of writing parameter values to the one or more degraded memory cells to compensate for the degradation of the one or more degraded memory cells and by applying the second set of writing parameter values to the undegraded memory cell.

16 . The system of claim 15 , wherein the plurality of memory cells comprise resistive memory cells.

17 . The system of claim 15 , wherein detecting the degradation of one or more degraded memory cells comprises:
determining, using a degradation model, storing conductance values that are different from written conductance values, wherein the degradation model processes the plurality of memory cells using as input a value of maximum resistance and the written conductance values to generate a matrix of the storing conductance values.

18 . The system of claim 15 , wherein detecting the degradation of one or more degraded memory cells comprises:
scanning, using a current meter, a conductance value of each memory cell of the plurality of memory cells; and determining a conductance change by comparing the conductance value of each memory cell to a previous conductance value stored by a buffer.

19 . The system of claim 15 , wherein the first set of writing parameter values and the second set of writing parameter values comprise a current, a voltage, a signal frequency or a pulse width.

20 . The system of claim 15 , wh

Assignees

• Univ California
• Texas A&M Univ

Inventors

• Dang Dharanidhar
• Sahoo Debashis
• Lin Bill
• Mahapatra Rabi
• Khansama Aurosmita
• Govardan Sudharsan

Classifications

• G11C11/54 Primary

  using elements simulating biological cells, e.g. neuron · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0035 Primary

  Evaluating degradation, retention or wearout, e.g. by counting writing cycles · CPC title

• G06N3/065

  Analogue means · CPC title

• G06N3/084

  Backpropagation, e.g. using gradient descent · CPC title