Semiconductor Device and Method of Manufacturing Same

Patent metadata

Field	Value
Publication number	US-2023255038-A1
Application number	US-202118012359-A
Country	US
Kind code	A1
Filing date	Oct 8, 2021
Priority date	Oct 29, 2020
Publication date	Aug 10, 2023
Grant date	—

Abstract

Provided is a semiconductor device and a method of manufacturing the semiconductor device that is capable of improving the connection reliability between an electronic element and a substrate in a semiconductor device in which the electronic element is fixed to the substrate. The semiconductor device includes: a substrate 10 provided with wirings and wiring connection parts 12 connected to the wirings; electronic elements 20, 30, 40, and 50 electrically connected to the wiring connection parts 12 and fixed to the substrate; and a resin film 60 laminated on one surface of the substrate 10, conforming to the shapes of the electronic elements 20, 30, 40, and 50, and covering the electronic elements 20, 30, 40, and 50.

First claim

1 . A semiconductor device comprising:
a substrate provided with a wiring and a wiring connection part connected to the wiring; an electronic element electrically connected to the wiring connection part and fixed to the substrate; and a resin film laminated on one surface of the substrate, the resin film conforming to a shape of the electronic element and covering the electronic element.

2 . The semiconductor device according to claim 1 , wherein the substrate is a flexible substrate.

3 . The semiconductor device according to claim 1 , wherein the wiring and the wiring connection part are formed of the same material.

4 . The semiconductor device according to claim 3 , wherein the wiring and the wiring connection part are formed with the same thickness.

5 . The semiconductor device according to claim 1 , wherein the electronic element comprises an organic semiconductor element.

6 . The semiconductor device according to claim 1 , wherein the substrate is a multilayer wiring substrate.

7 . The semiconductor device according to claim 1 , wherein the resin film is further laminated on the other surface of the substrate.

8 . A method of manufacturing a semiconductor device, the method comprising:
providing a substrate with a wiring and a wiring connection part connected to the wiring; electrically connecting an electronic element to the wiring connection part and fixing the electronic element to the substrate; and laminating a resin film on one surface of the substrate, the resin film conforming to a shape of the electronic element and covering the electronic element.

9 . The method of manufacturing a semiconductor device according to claim 8 , wherein the substrate is a flexible substrate.

10 . The method of manufacturing a semiconductor device according to claim 8 , wherein the wiring and the wiring connection part are formed simultaneously in the step of providing a substrate with a wiring and a wiring connection part connected to the wiring.

11 . The method of manufacturing a semiconductor device according to claim 10 , wherein the wiring and the wiring connection part are formed by printing in the step of providing a substrate with a wiring and a wiring connection part connected to the wiring.

12 . The method of manufacturing a semiconductor device according to claim 8 , wherein the resin film is laminated on one surface of the substrate in a vacuum or reduced pressure space in the step of laminating a resin film on one surface of the substrate.

13 . The method of manufacturing a semiconductor device according to claim 8 , wherein the resin film is laminated on one surface of the substrate in a state where a pressure in a space on the substrate side of the resin film is lower than a pressure in a space on the opposite side of the resin film from the substrate in the step of laminating a resin film on one surface of the substrate.

Assignees

• Univ Tokyo
• Pi Crystal Inc
• Organo Circuit Inc

Inventors

• Takeya Junichi
• Watanabe Kazuyoshi
• NOZAWA Han
• Ono Yuichi

Classifications

• H10W70/69

  Insulating materials thereof · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title