Method Of Handling Irregular MetaBlock Wear Leveling And UGSD Boot Time Improvement

US2023251788A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023251788-A1
Application numberUS-202217650490-A
CountryUS
Kind codeA1
Filing dateFeb 9, 2022
Priority dateFeb 9, 2022
Publication dateAug 10, 2023
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure generally relates to using irregular MetaBlocks (IRMBs) in both host and control pools. The IRMBs are used to ensure efficient wear leveling. Blocks in the control pool are swapped with blocks in the host pool upon exceeding a program-erase count (PEC) threshold. Additionally, the swapping algorithm for IRMBs can be used to ensure an efficient recovery from an ungraceful shutdown (UGSD) event.

First claim

Opening claim text (preview).

What is claimed is: 1 . A data storage device, comprising: a memory device; and a controller coupled to the memory device, the controller configured to: arrange one or more host pools comprising a first plurality of MetaBlocks, wherein each MetaBlock of the first plurality comprises at least two blocks; arrange one or more control pools comprising a second plurality of MetaBlocks, wherein each MetaBlock of the second plurality comprises at least two blocks, wherein at least one MetaBlock of the control pool is an irregular MetaBlock (IRMB); and swap one or more blocks from the control pool with one or more blocks of the host pool to create a new MetaBlock. 2 . The data storage device of claim 1 , wherein the controller is further configured to determine that one or more thresholds is exceeded prior to the swapping. 3 . The data storage device of claim 1 , wherein the controller is configured to determine which MetaBlock in the host pool has a highest program-erase count (PEC). 4 . The data storage device of claim 3 , wherein the controller is configured to determine which MetaBlock in the control pool has a lowest PEC. 5 . The data storage device of claim 4 , wherein the controller is further configured to compare a difference between the MetaBlock in the host pool having the highest PEC and the MetaBlock in the control pool having the lowest PEC. 6 . The data storage device of claim 5 , wherein the controller is further configured to compare the difference to a threshold. 7 . The data storage device of claim 1 , wherein the controller is configured to determine whether data in the one or more blocks of the host pool that is swapped is valid. 8 . The data storage device of claim 1 , wherein the swapping comprises relocating data from the one or more host blocks to the one or more control blocks. 9 . The data storage device of claim 1 , wherein after the swapping, at least two blocks of the created new MetaBlock have different program-erase counts. 10 . The data storage device of claim 1 , wherein the swapping additionally comprises moving one or more blocks from a MetaBlock in the host pool to a different MetaBlock in the host pool. 11 . The data storage device of claim 10 , wherein the created new MetaBlock comprises at least one block having a different program-erase count (PEC) compared to at least one other block of the created new MetaBlock. 12 . The data storage device of claim 1 , wherein the controller is configured to detect that an ungraceful shutdown (UGSD) has occurred. 13 . The data storage device of claim 12 , wherein the swapping is in response to detecting the UGSD. 14 . A data storage device, comprising: a memory device; and a controller coupled to the memory device, the controller configured to: detect that an ungraceful shutdown (UGSD) has occurred; determine that a first irregular MetaBlock (IRMB) experienced a write abort during the UGSD, wherein less than all blocks of the first IRMB experienced the write abort; create a second IRMB, wherein the second IRMB comprises blocks that experienced the write abort and blocks that are unallocated; and create a third IRMB, wherein the third IRMB comprises remaining blocks from the first IRMB and additional unallocated blocks. 15 . The data storage device of claim 14 , wherein the second IRMB and the third IRMB are in a control pool. 16 . The data storage device of claim 15 , wherein the unallocated blocks and the additional unallocated blocks are disposed in a control pool. 17 . The data storage device of claim 14 , wherein the first IRMB is in a control pool. 18 . The data storage device of claim 14 , wherein the controller is further configured to copy data from the blocks that experienced the write abort to the additional unallocated blocks. 19 . A data storage device, comprising: memory means; and a controller coupled to the memory means, the controller configured to: dynamically create irregular MetaBlocks (IRMBs) using blocks from one or more IRMBs in a control pool based upon a program-erase count (PEC) difference between a host pool and the control pool. 20 . The data storage device of claim 19 , wherein the controller is further configured to swap all eligible PEC MetaBlocks from the control pool with eligible PEC MetaBlocks from the host pool upon exceeding a PEC threshold.

Assignees

Inventors

Classifications

  • G06F3/0616Primary

    in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • G06F3/064Primary

    Management of blocks · CPC title

  • Lifecycle management · CPC title

  • Improving or facilitating administration, e.g. storage management · CPC title

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Frequently asked questions

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What does patent US2023251788A1 cover?
The present disclosure generally relates to using irregular MetaBlocks (IRMBs) in both host and control pools. The IRMBs are used to ensure efficient wear leveling. Blocks in the control pool are swapped with blocks in the host pool upon exceeding a program-erase count (PEC) threshold. Additionally, the swapping algorithm for IRMBs can be used to ensure an efficient recovery from an ungraceful …
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/0616. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Aug 10 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).