Semiconductor device and three-phase inverter comprising the same

Patent metadata

Field	Value
Publication number	US-2023246095-A1
Application number	US-202217835367-A
Country	US
Kind code	A1
Filing date	Jun 8, 2022
Priority date	Feb 3, 2022
Publication date	Aug 3, 2023
Grant date	—

Abstract

Provided is a semiconductor device including a semiconductor substrate, a plurality of gate electrodes disposed on the upper surface portion of the semiconductor substrate and spaced apart from each other, a plurality of emitter electrodes disposed to be overlapped with each of the plurality of gate electrodes, and a collector electrode disposed on the lower surface of the semiconductor substrate.

First claim

1 . A semiconductor device, comprising:
a semiconductor substrate; a plurality of gate electrodes positioned on an upper surface portion of the semiconductor substrate and spaced apart from each other; a plurality of emitter electrodes positioned overlapping with each of the plurality of gate electrodes; and a collector electrode positioned on a lower surface of the semiconductor substrate.

2 . The semiconductor device of claim 1 , wherein the semiconductor device includes three gate electrodes, three emitter electrodes, and one collector electrode as one set.

3 . The semiconductor device of claim 1 , wherein the semiconductor device is positioned on the upper surface portion of the semiconductor substrate and includes a plurality of second conductivity-type impurity regions connected to the plurality of emitter electrodes.

4 . The semiconductor device of claim 3 , wherein two second conductivity-type impurity regions are connected to one emitter electrode.

5 . The semiconductor device of claim 3 , further comprising a first conductivity-type well region disposed on the upper surface portion of the semiconductor substrate; and
the plurality of second conductivity-type impurity regions are positioned in the first conductivity-type well region.

6 . The semiconductor device of claim 4 , further comprising a plurality of first conductivity-type well regions; and
the pair of second conductivity-type impurity regions are positioned in the first conductivity-type well regions.

7 . The semiconductor device of claim 4 , further comprising a plurality of first conductivity-type well regions; and
two second conductivity-type impurity regions connected to adjacent emitter electrodes positioned in the first conductivity-type well region.

8 . The semiconductor device of claim 3 , further comprising a plurality of first conductivity-type well regions, wherein each of the second conductivity-type impurity regions is positioned in each of the first conductivity-type well regions.

9 . The semiconductor device of claim 1 , further comprising a plurality of trenches that are opened to the upper surface, wherein each of the plurality of gate electrodes is positioned in each of the plurality of trenches.

10 . The semiconductor device of claim 9 , wherein the each of the plurality of trench divides two second conductivity-type impurity regions connected to one emitter electrode.

11 . The semiconductor device of claim 1 , further comprising a collector layer positioned between the semiconductor substrate and the collector electrode.

12 . The semiconductor device of claim 1 , wherein the semiconductor device is an insulated gate bipolar transistor (IGBT).

13 . An inverter comprising:
in a 3 -phase inverter circuit for supplying 3-phase power by converting an input voltage, a first semiconductor device including three gate electrodes and three emitter electrodes; and a second semiconductor device including three gate electrodes and three emitter electrodes; an input voltage supplied between a collector electrode of the first semiconductor device and a collector electrode of the second semiconductor device, and a three-phase load connected to three contact points to which the three emitter electrodes of the first semiconductor device and the three emitter electrodes of the second semiconductor device are connected; and in each of the first semiconductor device and the second semiconductor device, the three gate electrodes are positioned on one surface of the semiconductor substrate and are spaced apart from each other, the three emitter electrodes are positioned to be overlapping with each of the three gate electrodes, and the collector electrode is positioned on an other surface of the semiconductor substrate.

Assignees

• Hyundai Motor Co Ltd
• Kia Corp

Inventors

• Joo Nackyong
• Chun Dae Hwan
• Hong Jungyeop
• Jung Youngkyun
• Park Junghee

Classifications

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D12/411 Primary

  Insulated-gate bipolar transistors [IGBT] · CPC title

• H10D64/232

  Emitter electrodes for IGBTs · CPC title