Slave-initiated communications over a single-wire bus

Patent metadata

Field	Value
Publication number	US-2023229616-A1
Application number	US-202318154127-A
Country	US
Kind code	A1
Filing date	Jan 13, 2023
Priority date	Jan 20, 2022
Publication date	Jul 20, 2023
Grant date	—

Abstract

Slave-initiated communications over a single-wire bus are described in the present disclosure. In contrast to a conventional single-wire bus apparatus wherein communications over the single-wire bus are always initiated by a master circuit, a single-wire bus apparatus disclosed herein allows a slave circuit(s) to initiate communications over the single-wire bus. More specifically, multiple slave circuits can concurrently contend for access to the single-wire bus via current mode signaling (CMS). In response to the CMS asserted by the multiple slave circuits, a master circuit provides a number of pulse-width modulation (PWM) symbols over the single-wire bus to indicate which of the multiple slave circuits is granted access to the single-wire bus. By supporting slave-initiated communications over the single-wire bus, it is possible to improve efficiency, cost, and power consumption in an electronic device (e.g., smartphone) wherein the single-wire bus apparatus is deployed.

First claim

What is claimed is:

1 . A single-wire bus apparatus comprising:
a single-wire bus consisting of one wire; and a plurality of slave circuits each coupled to the single-wire bus and uniquely identified by a unique slave identification (USID) comprising multiple bits; wherein one or more slave circuits among the plurality of slave circuits are each configured to:
assert a wakeup current mode signaling (CMS) on the single-wire bus to indicate a request to communicate a data telegram over the single-wire bus in response to a respective data trigger;
receive a plurality of pulse-width modulation (PWM) symbols via the single-wire bus in response to asserting the wakeup CMS;
determine whether the request is successful based on the plurality of received PWM symbols; and
communicate the data telegram over the single-wire bus in response to determining that the request is successful.

2 . The single-wire bus apparatus of claim 1 , further comprising a master circuit coupled to the single-wire bus and configured to:
detect the wakeup CMS asserted by the one or more slave circuits; transmit a start-of-sequence (SOS) sequence over the single-wire bus in response to detecting the wakeup CMS asserted by the one or more slave circuits; and transmit the plurality of PWM symbols via the single-wire bus in an arbitration interval after transmitting the SOS sequence.

3 . The single-wire bus apparatus of claim 2 , wherein the plurality of PWM symbols comprises a priority symbol and a plurality of USID bit symbols succeeding the priority symbol.

4 . The single-wire bus apparatus of claim 3 , wherein the master circuit is further configured to:
modulate the priority symbol and a respective one of the plurality of USID bit symbols to represent a binary one in response to detecting a bit indication CMS in the priority symbol and the respective one of the plurality of USID bit symbols; and modulate the priority symbol and the respective one of the plurality of USID bit symbols to represent a binary zero in response to not detecting the bit indication CMS in the priority symbol and the respective one of the plurality of USID bit symbols.

5 . The single-wire bus apparatus of claim 3 , wherein the request is determined to be successful by a respective one of the one or more slave circuits if the plurality of USID bit symbols collectively indicate the multiple bits in the USID that uniquely identify the respective one of the one or more slave circuits.

6 . The single-wire bus apparatus of claim 5 , wherein each of the plurality of USID bit symbols represents a respective one of the multiple bits in the USID and a first one of the plurality of USID bit symbols immediately succeeding the priority symbol represents a most significant bit (MSB) of the USID.

7 . The single-wire bus apparatus of claim 6 , wherein, in a first attempt to contend for the single-wire bus, the respective one of the one or more slave circuits is further configured to:
assert a bit indication CMS in a respective one of the plurality of USID bit symbols if a respective one of the multiple bits in the USID that uniquely identifies the respective one of the one or more slave circuits is equal to one; and not assert the bit indication CMS in the respective one of the plurality of USID bit symbols if the respective one of the multiple bits in the USID that uniquely identifies the respective one of the one or more slave circuits is equal to zero.

8 . The single-wire bus apparatus of claim 7 , wherein the respective one of the one or more slave circuits is further configured not to assert the bit indication CMS in the priority symbol in the first attempt to contend for the single-wire bus.

9 . The single-wire bus apparatus of claim 5 , wherein the respective one of the one or more slave circuits is further configured not to assert a bit indication CMS in the priority symbol when the request is determined to be successful.

10 . The single-wire bus apparatus of claim 6 , wherein, in response to an unsuccessful attempt to contend for the single-wire bus, the respective one of the one or more slave circuits is further configured to:
assert a bit indication CMS in the priority symbol; assert the bit indication CMS in a respective one of the plurality of USID bit symbols if a respective one of the multiple bits in the USID that uniquely identifies the respective one of the one or more slave circuits is equal to one; and not assert the bit indication CMS in the respective one of the plurality of USID bit symbols if the respective one of the multiple bits in the USID that uniquely identifies the respective one of the one or more slave circuits is equal to zero.

11 . The single-wire bus apparatus of claim 1 , wherein each of the plurality of slave circuits is configured to harvest power via the single-wire bus while one of the plurality of slave circuits communicates the data telegram over the single-wire bus.

12 . A method for supporting slave-initiated communications over a single-wire bus comprising:
asserting a wakeup current mode signaling (CMS) on the single-wire bus to indicate a request to communicate a data telegram over the single-wire bus in response to a respective data trigger; receiving a plurality of pulse-width modulation (PWM) symbols via the single-wire bus in response to asserting the wakeup CMS; determining whether the request is successful based on the plurality of received PWM symbols; and communicating the data telegram over the single-wire bus in response to determining that the request is successful.

13 . The method of claim 12 , further comprising:
detecting the wakeup CMS; transmitting a start-of-sequence (SOS) sequence over the single-wire bus in response to detecting the wakeup CMS; and transmitting the plurality of PWM symbols via the single-wire bus in an arbitration interval after transmitting the SOS sequence.

14 . The method of claim 13 , further comprising:
modulating a priority symbol and a respective one of a plurality of USID bit symbols succeeding the priority symbol in the plurality of PWM symbols to represent a binary one in response to detecting a bit indication CMS in the priority symbol and the respective one of the plurality of USID bit symbols; and modulating the priority symbol and the respective one of the plurality of USID bit symbols to represent a binary zero in response to not detecting the bit indication CMS in the priority symbol and the respective one of the plurality of USID bit symbols.

15 . The method of claim 14 , further comprising determining the request as being successful if the plurality of USID bit symbols collectively indicates multiple bits in the USID that uniquely identify a respective one of one or more slave circuits.

16 . The method of claim 15 , further comprising, in a first attempt to contend for the single-wire bus:
asserting a bit indication CMS in a respective one of the plurality of USID bit symbols if a respective one of the multiple bits in the USID is equal to one; and not asserting the bit indication CMS in the respective one of the plurality of USID bit symbols if the respective one of the multiple bits in the USID is equal to zero.

17 . The method of claim 16 , further comprising not asserting the bit indication CMS in the priority symbol in the first attempt to contend for the single-wire bus.

18 . The method of claim 15 , further comprising not asserting a bit indication CMS in the priority symbol when the request is determined to be successful.

19 . The

Assignees

• Qorvo Us Inc

Inventors

• Ngo Christopher Truong
• Hietala Alexander Wayne
• Khlat Nadim

Classifications

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04L12/403 Primary

  with centralised control, e.g. polling · CPC title