Code processing method and apparatus, and storage medium

US2023229410A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023229410-A1
Application numberUS-202318185894-A
CountryUS
Kind codeA1
Filing dateMar 17, 2023
Priority dateSep 21, 2020
Publication dateJul 20, 2023
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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This application discloses code processing methods, apparatuses, and storage media. An example method includes: obtaining a first code in low-level language and applicable to a source platform; decompiling the obtained first code to obtain an intermediate representation (IR); and then compiling the IR into a second code in low-level language and applicable to a first target platform, where the source platform and the target platform have different instruction sets.

First claim

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1 . A method, wherein the method comprises: obtaining a first code in low-level language and applicable to a source platform; decompiling the first code to obtain a first intermediate representation (IR); and compiling the first IR into a second code in low-level language and applicable to a first target platform, wherein the source platform and the first target platform have different instruction sets. 2 . The method according to claim 1 , wherein the method further comprises: decompiling the first code to obtain a second IR corresponding to a second target platform, wherein the first target platform and the second target platform have different instruction sets. 3 . The method according to claim 1 , wherein the method further comprises: presenting a target platform selection interface; and determining the first target platform from a plurality of target platforms in response to a selection operation on a target platform through the target platform selection interface. 4 . The method according to claim 1 , wherein the decompiling the first code to obtain a first IR comprises: obtaining annotation information of the first code, wherein the annotation information comprises one or more of a type, a quantity, or a jump address type of a parameter in the first code; and decompiling the first code based on the annotation information, to obtain the first IR. 5 . The method according to claim 1 , wherein the decompiling the first code to obtain a first IR comprises: decompiling the first code to obtain a second IR; and optimizing the second IR based on the first target platform, to obtain the first IR. 6 . The method according to claim 1 , wherein the method further comprises: generating prompt information that prompts for a to-be-checked item to be generated based on a difference between the first target platform and the source platform; and presenting the prompt information. 7 . The method according to claim 1 , wherein the method is applied to a cloud, wherein the first code is obtained from a user, and wherein the method further comprises: sending the second code to the user. 8 . The method according to claim 1 , wherein the decompiling the first code comprises: decompiling the first code based on an instruction semantic library corresponding to the source platform. 9 . The method according to claim 8 , wherein the method further comprises: modifying the instruction semantic library in response to a modification operation on the instruction semantic library. 10 . The method according to claim 1 , wherein the obtaining a first code in low-level language and applicable to a source platform comprises: obtaining the first code in low-level language and applicable to the source platform and a variable in high-level language; and the decompiling the first code comprises: translating the first code into the first IR, wherein the variable is an actual parameter corresponding to a formal parameter in a function of the first IR. 11 . The method according to claim 1 , wherein the first IR comprises a first variable and a second variable, the first variable has a first logical address, the second variable has a second logical address different from the first logical address. 12 . The method according to claim 1 , wherein the decompiling the first code comprises: decompiling the first code based on a function calling convention or a single instruction multiple data (SIMD) instruction of the first target platform. 13 . A computing apparatus, wherein the computing apparatus comprises at least one memory and at least one processor, the at least one memory is coupled to the at least one processor, and the at least one memory stores programming instructions for execution by the at least one processor to cause the computing apparatus to perform operations comprising: obtaining a first code in low-level language and applicable to a source platform; decompiling the first code to obtain a first intermediate representation (IR); and compiling the first IR into a second code in low-level language and applicable to a first target platform, wherein the source platform and the first target platform have different instruction sets. 14 . The computing apparatus of claim 13 , wherein the operations further comprise: decompiling the first code to obtain a second IR corresponding to a second target platform, wherein the first target platform and the second target platform have different instruction sets. 15 . The computing apparatus of claim 13 , wherein the operations further comprise: presenting a target platform selection interface; and determining the first target platform from a plurality of target platforms in response to a selection operation on a target platform through the target platform selection interface. 16 . The computing apparatus of claim 13 , wherein the decompiling the first code to obtain a first IR comprises: obtaining annotation information of the first code, wherein the annotation information comprises one or more of a type, a quantity, or a jump address type of a parameter in the first code; and decompiling the first code based on the annotation information, to obtain the first IR. 17 . The computing apparatus of claim 13 , wherein the decompiling the first code to obtain a first IR comprises: decompiling the first code to obtain a second IR; and optimizing the second IR based on the first target platform, to obtain the first IR. 18 . The computing apparatus of claim 13 , wherein the operations further comprise: generating prompt information that prompts for a to-be-checked item to be generated based on a difference between the first target platform and the source platform; and presenting the prompt information. 19 . The computing apparatus of claim 13 , wherein the first code is obtained from a user, and wherein the operations further comprise: sending the second code to the user. 20 . A non-volatility computer-readable storage medium comprising programming instructions for execution by at least one processor of a computing apparatus to cause the computing apparatus to perform operations comprising: obtaining a first code in low-level language and applicable to a source platform; decompiling the first code to obtain a first intermediate representation (IR); and compiling the first IR into a second code in low-level language and applicable to a first target platform, wherein the source platform and the first target platform have different instruction sets.

Assignees

Inventors

Classifications

  • Adapting program code to run in a different environment; Porting · CPC title

  • G06F8/53Primary

    Decompilation; Disassembly · CPC title

  • G06F8/51Primary

    Source to source · CPC title

  • Dependency analysis; Data or control flow analysis · CPC title

  • Compilation · CPC title

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What does patent US2023229410A1 cover?
This application discloses code processing methods, apparatuses, and storage media. An example method includes: obtaining a first code in low-level language and applicable to a source platform; decompiling the obtained first code to obtain an intermediate representation (IR); and then compiling the IR into a second code in low-level language and applicable to a first target platform, where the …
Who is the assignee on this patent?
Huawei Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F8/53. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jul 20 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).