Internal node jumper for memory bit cells

Patent metadata

Field	Value
Publication number	US-2023223339-A1
Application number	US-202318119225-A
Country	US
Kind code	A1
Filing date	Mar 8, 2023
Priority date	Jun 20, 2017
Publication date	Jul 13, 2023
Grant date	—

Abstract

Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a memory bit cell, comprising:
first, second, third and fourth three-dimensional semiconductor bodies parallel along a first direction;
first and second gate lines over the first, second, third and fourth three-dimensional semiconductor bodies, the first and second gate lines each around one or more of the first, second, third and fourth three-dimensional semiconductor bodies, and the first and second gate lines parallel along a second direction, the second direction perpendicular to the first direction; and
first, second and third interconnect lines over the first and second gate lines, the first, second and third interconnect lines parallel along the second direction, wherein the first and second interconnect lines are electrically connected to the first and second gate lines at locations of the first and second gate lines over one or more of the first, second, third and fourth three-dimensional semiconductor bodies, wherein the third interconnect line electrically couples together a pair of gate electrodes of the memory bit cell or electrically couples together a pair of trench contacts of the memory bit cell, and wherein one of the first, second or third interconnect lines is vertically overlapping with one of the first or second gate lines.

2 . The integrated circuit structure of claim 1 , wherein the third interconnect line electrically couples together the pair of gate electrodes of the memory bit cell.

3 . The integrated circuit structure of claim 1 , wherein the third interconnect line electrically couples together the pair of trench contacts of the memory bit cell.

4 . The integrated circuit structure of claim 1 , wherein the first three-dimensional semiconductor body is a P-type doped three-dimensional semiconductor body, the second three-dimensional semiconductor body is an N-type doped three-dimensional semiconductor body, the third three-dimensional semiconductor body is an N-type doped three-dimensional semiconductor body, and the fourth three-dimensional semiconductor body is an N-type doped three-dimensional semiconductor body.

5 . The integrated circuit structure of claim 1 , wherein the first and second gate lines alternate with individual ones of a plurality of trench contact lines parallel along the second direction, the plurality of trench contact lines comprising the pair of trench contacts of the memory bit cell.

6 . The integrated circuit structure of claim 1 , wherein the first and second gate lines have a first pitch along the first direction, the first, second and third interconnect lines have a second pitch along the first direction, and wherein the second pitch is less than the first pitch.

7 . The integrated circuit structure of claim 1 , wherein the first pitch is in the range of 50 nanometers to 60 nanometers, and wherein the second pitch is in the range of 30 nanometers to 40 nanometers.

8 . The integrated circuit structure of claim 1 , wherein the first and second interconnect lines are electrically connected to the first and second gate lines by an intervening plurality of interconnect lines between the first and second interconnect lines and the first and second gate lines, and wherein the intervening plurality of interconnect lines is parallel along the first direction.

9 . An integrated circuit structure, comprising:
a three-dimensional body comprising silicon; a first gate electrode and a second gate electrode over the three-dimensional body, the first gate electrode and the second gate electrode around the three-dimensional body, the first and second gate electrodes along a first direction, and the first and second gate electrodes having a first pitch; a first plurality of metal lines above the first and second gate electrodes; a gate contact coupling one of the first plurality of metal lines to the first gate electrode at a location vertically over the three-dimensional body; a second plurality of metal lines over the first plurality of metal lines, wherein metal lines of the second plurality of metal lines are along the first direction and have a second pitch, the second pitch less than the first pitch, and wherein one of the second plurality of metal lines is vertically overlapping with one of the first or second gate electrodes.

10 . The integrated circuit structure of claim 9 , wherein the second pitch is approximately 0.67 times the first pitch.

11 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a memory bit cell, comprising:
first, second, third and fourth three-dimensional semiconductor bodies parallel along a first direction;
first and second gate lines over the first, second, third and fourth three-dimensional semiconductor bodies, the first and second gate lines each around one or more of the first, second, third and fourth three-dimensional semiconductor bodies, and the first and second gate lines parallel along a second direction, the second direction perpendicular to the first direction; and
first, second and third interconnect lines over the first and second gate lines, the first, second and third interconnect lines parallel along the second direction, wherein the first and second interconnect lines are electrically connected to the first and second gate lines at locations of the first and second gate lines over one or more of the first, second, third and fourth three-dimensional semiconductor bodies, wherein the third interconnect line electrically couples together a pair of gate electrodes of the memory bit cell or electrically couples together a pair of trench contacts of the memory bit cell, and wherein one of the first, second or third interconnect lines is vertically overlapping with one of the first or second gate lines.

12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14 . The computing device of claim 11 , further comprising:
a battery coupled to the board.

15 . The computing device of claim 11 , further comprising:
a camera coupled to the board.

16 . The computing device of claim 11 , further comprising:
a compass coupled to the board.

17 . The computing device of claim 11 , further comprising:
a GPS coupled to the board.

18 . The computing device of claim 11 , further comprising:
a touchscreen display coupled to the board.

19 . The computing device of claim 11 , further comprising:
a speaker coupled to the board.

20 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Shridharan Smita
• Guo Zheng
• Karl Eric A
• Shchupak George
• Kosinovsky Tali

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10B10/12 Primary

  comprising a MOSFET load element · CPC title

• G11C5/02 Primary

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title