Silicon carbide semiconductor device and power converter

Patent metadata

Field	Value
Publication number	US-2023215921-A1
Application number	US-202018008448-A
Country	US
Kind code	A1
Filing date	Aug 11, 2020
Priority date	Aug 11, 2020
Publication date	Jul 6, 2023
Grant date	—

Abstract

A silicon carbide layer has an active region and an outer peripheral region arranged along an outer periphery of the active region in an in-plane direction. First well regions are arranged in the active region. A second well region is arranged in the outer peripheral region. Ohmic electrodes are arranged on a second surface of the silicon carbide layer, are connected to a source electrode, are electrically and ohmically connected to the first well regions, and have surface regions ohmically contacting a part forming the second surface of the silicon carbide layer and having a second conductivity type. The active region includes a standard region part and a thinned region part between the standard region part and the outer peripheral region. The surface regions are arranged at surface density lower in the thinned region part than in the standard region part in a plan view.

First claim

1 . A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first conductivity type; a silicon carbide layer having a first surface facing the silicon carbide substrate and a second surface opposite the first surface in a thickness direction, and having an active region and an outer peripheral region arranged along an outer periphery of the active region in an in-plane direction vertical to the thickness direction, the silicon carbide layer including:
a drift layer arranged on the silicon carbide substrate and having the first conductivity type;
a plurality of first well regions arranged on the drift layer in the active region, having a second conductivity type different from the first conductivity type, and separated from each other at least in one sectional view;
a plurality of source regions arranged on the first well regions and having the first conductivity type; and
a second well region arranged on the drift layer in the outer peripheral region and having the second conductivity type;
a gate insulating film facing the first well regions; a gate electrode having a part that is arranged over the active region and faces the first well regions across the gate insulating film, and a part that is arranged over the outer peripheral region and insulated from the second well region; a gate pad arranged over the second well region, insulated from the second well region, and connected to the gate electrode; a source electrode provided over the second surface of the silicon carbide layer; and a plurality of ohmic electrodes provided on the second surface of the silicon carbide layer, connected to the source electrode, electrically and ohmically connected to the first well regions, and having a plurality of surface regions ohmically contacting a part of the second surface of the silicon carbide layer, the part of the second surface of the silicon carbide layer having the second conductivity type, wherein the active region includes a standard region part and a thinned region part between the standard region part and the outer peripheral region, the surface regions being arranged at surface density lower in the thinned region part than in the standard region part in a plan view, and wherein the thinned region part has a width that is equal to or greater than 20% of a sum of the thickness of the silicon carbide substrate and the thickness of the silicon carbide layer, the width corresponding to a distance between the standard region part and the outer peripheral region.

2 . The silicon carbide semiconductor device according to claim 1 , wherein
the ohmic electrodes are arranged at positions displaced from a position over the second well region.

3 . The silicon carbide semiconductor device according to claim 1 , wherein
the first well regions are arranged in a stripe pattern in the in-plane direction.

4 . The silicon carbide semiconductor device according to claim 1 , wherein
in the in-plane direction, the first well regions have polygonal shapes arranged repeatedly in the standard region part.

5 .- 6 . (canceled)

7 . The silicon carbide semiconductor device according to claim 1 , wherein
the surface density in the thinned region part is equal to or greater than 1/10 and equal to or less than ⅔ of the surface density in the active region.

8 . The silicon carbide semiconductor device according to claim 1 , wherein
the surface density in the thinned region part is reduced further with a shorter distance to an external side.

9 . The silicon carbide semiconductor device according to claim 1 , wherein
the surface density in the thinned region part has several levels.

10 . The silicon carbide semiconductor device according to claim 1 , wherein
current density in an ON state is equal to or greater than 100 A/cm 2 .

11 . A power converter comprising:
a main conversion circuit that includes the silicon carbide semiconductor device according to claim 1 , accepts input power, converts the input power to output power, and provides the output power; a driving circuit that outputs a driving signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; and a control circuit that outputs a control signal for controlling the driving circuit to the driving circuit.

12 . A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first conductivity type; a silicon carbide layer having a first surface facing the silicon carbide substrate and a second surface opposite the first surface in a thickness direction, and having an active region and an outer peripheral region arranged along an outer periphery of the active region in an in-plane direction vertical to the thickness direction, the silicon carbide layer including:
a drift layer arranged on the silicon carbide substrate and having the first conductivity type;
a plurality of first well regions arranged on the drift layer in the active region, having a second conductivity type different from the first conductivity type, and separated from each other at least in one sectional view;
a plurality of source regions arranged on the first well regions and having the first conductivity type; and
a second well region arranged on the drift layer in the outer peripheral region and having the second conductivity type;
a gate insulating film facing the first well regions; a gate electrode having a part that is arranged over the active region and faces the first well regions across the gate insulating film, and a part that is arranged over the outer peripheral region and insulated from the second well region; a gate pad arranged over the second well region, insulated from the second well region, and connected to the gate electrode; a source electrode provided over the second surface of the silicon carbide layer; and a plurality of ohmic electrodes provided on the second surface of the silicon carbide layer, connected to the source electrode, electrically and ohmically connected to the first well regions, and having a plurality of surface regions ohmically contacting a part of the second surface of the silicon carbide layer, the part of the second surface of the silicon carbide layer having the second conductivity type, wherein the active region includes a standard region part and a thinned region part between the standard region part and the outer peripheral region, the surface regions being arranged at surface density lower in the thinned region part than in the standard region part in a plan view, and wherein the ohmic electrodes are arranged at positions displaced from a position over the second well region.

13 . A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first conductivity type; a silicon carbide layer having a first surface facing the silicon carbide substrate and a second surface opposite the first surface in a thickness direction, and having an active region and an outer peripheral region arranged along an outer periphery of the active region in an in-plane direction vertical to the thickness direction, the silicon carbide layer including:
a drift layer arranged on the silicon carbide substrate and having the first conductivity type;
a plurality of first well regions arranged on the drift layer in the active region, having a second conductivity type different from the first conductivity type, and separated from each other at least in one sectional view;
a plurality of source regions arranged on the first well regions and having the first conductivity type; and
a second well region arranged on the drift layer in the outer peripheral region and having t

Assignees

• Mitsubishi Electric Corp

Inventors

• NAGAHISA Yuichi
• Tanaka Takanori
• Amishiro Hiroyuki
• Kawabata Naoyuki

Classifications

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D12/031

  of IGBTs · CPC title

• H10D62/8325 Primary

  Silicon carbide · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title