Communication repeater and method for restoring synchronization thereof

US2023199682A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023199682-A1
Application numberUS-202218145409-A
CountryUS
Kind codeA1
Filing dateDec 22, 2022
Priority dateDec 22, 2021
Publication dateJun 22, 2023
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

Provided is a communication repeater including a receiver configured to receive a plurality of test signals from a plurality of external communication devices and then receive a plurality of downlink signals from the plurality of external communication devices, and a digital signal processor configured to measure a delay time of each of the plurality of test signals and perform a delay synchronization process for the plurality of downlink signals, wherein the digital signal processor is configured to determine whether the plurality of downlink signals for which the delay synchronization process has been performed are synchronized, and perform synchronization restoration for a downlink signal having a synchronization error among the plurality of downlink signals, based on a result of the determining.

First claim

Opening claim text (preview).

What is claimed is: 1 . A communication repeater comprising: a receiver configured to receive a plurality of test signals from a plurality of external communication devices and then receive a plurality of downlink signals from the plurality of external communication devices; and a digital signal processor configured to measure a delay time of each of the plurality of test signals and perform a delay synchronization process for the plurality of downlink signals, wherein the digital signal processor is configured to determine whether the plurality of downlink signals for which the delay synchronization process has been performed are synchronized, and perform synchronization restoration for a downlink signal having a synchronization error among the plurality of downlink signals, based on a result of the determining. 2 . The communication repeater of claim 1 , wherein the digital signal processor is configured to, when there is a downlink signal having the synchronization error, perform synchronization restoration for the downlink signal having the synchronization error based on other downlink signal correctly synchronized. 3 . The communication repeater of claim 2 , wherein the digital signal processor is configured to reproduce the other downlink signal correctly synchronized, and replace the downlink signal having the synchronization error with the reproduced downlink signal. 4 . The communication repeater of claim 1 , wherein the digital signal processor is configured to obtain a clock for each of the received plurality of test signals, and set one of the obtained plurality of clocks as a reference clock, and process a clock for each of the received plurality of downlink signals to correspond to the reference clock. 5 . The communication repeater of claim 4 , wherein the digital signal processor is configured to set one of the obtained plurality of clocks as the reference clock, based on a loss of signal (LoS) of each of the plurality of test signals. 6 . The communication repeater of claim 1 , wherein the digital signal processor is configured to perform a delay synchronization process on the plurality of downlink signals based on the longest of the delay times of the plurality of test signals. 7 . A method of restoring synchronization of a communication repeater, the method comprising: measuring a delay time of each of a plurality of test signals received from a plurality of external communication devices; performing a delay synchronization process for a plurality of downlink signals received from the plurality of external communication devices based on the measured delay times; determining whether the plurality of downlink signals for which the delay synchronization process has been performed are synchronized; and performing synchronization restoration for a downlink signal determined to have a synchronization error among the plurality of downlink signals. 8 . The method of claim 7 , wherein the performing of the synchronization restoration comprises performing synchronization restoration for a downlink signal having the synchronization error based on other downlink signal determined to be correctly synchronized among the plurality of downlink signals. 9 . The method of claim 8 , wherein the performing of the synchronization restoration comprises reproducing the other downlink signal determined to be correctly synchronized; and replacing the downlink signal having the synchronization error with the reproduced downlink signal. 10 . The method of claim 7 , further comprising: obtaining a clock for each of the received plurality of test signals, and set one of the obtained plurality of clocks as a reference clock; and processing a clock for each of the received plurality of downlink signals to correspond to the reference clock. 11 . The method of claim 10 , wherein the setting comprises setting one of the obtained plurality of clocks as the reference clock, based on a loss of signal (LoS) of each of the plurality of test signals. 12 . The method of claim 7 , wherein the performing of the delay synchronization process comprises performing a delay synchronization process on the plurality of downlink signals based on the longest of the delay times of the plurality of test signals.

Assignees

Inventors

Classifications

  • Cell enhancers {or enhancement}, e.g. for tunnels, building shadow · CPC title

  • compensating for timing error of reception due to propagation delay · CPC title

  • one node acting as a reference for the others · CPC title

  • H04W56/001Primary

    Synchronization between nodes · CPC title

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What does patent US2023199682A1 cover?
Provided is a communication repeater including a receiver configured to receive a plurality of test signals from a plurality of external communication devices and then receive a plurality of downlink signals from the plurality of external communication devices, and a digital signal processor configured to measure a delay time of each of the plurality of test signals and perform a delay synchron…
Who is the assignee on this patent?
Solid Inc
What technology area does this patent fall under?
Primary CPC classification H04W56/0015. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 22 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).