Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drain

Patent metadata

Field	Value
Publication number	US-2023197731-A1
Application number	US-202117644858-A
Country	US
Kind code	A1
Filing date	Dec 17, 2021
Priority date	Dec 17, 2021
Publication date	Jun 22, 2023
Grant date	—

Abstract

A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.

First claim

1 . A structure, comprising:
a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer; a first field effect transistor (FET) adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and a drain in the base semiconductor layer under the buried insulator layer, the second FET having a source and a drain over the buried insulator layer; and a trench isolation in each of the source and the drain of the first FET, the source of the first FET surrounding the trench isolation therein.

2 . The structure of claim 1 , wherein the buried insulator layer has a same composition and a same thickness in the first FET and the second FET.

3 . The structure of claim 1 , wherein the first FET operates at a higher voltage than the second FET.

4 . The structure of claim 1 , wherein the gate electrode of the first FET overlaps both trench isolations in the source and the drain of the first FET.

5 . The structure of claim 1 , wherein the gate electrode of the first FET includes an epitaxial semiconductor layer over the SOI layer.

6 . The structure of claim 5 , wherein the second FET includes a gate electrode over the SOI layer, and wherein the source and the drain of the second FET are positioned at least in part in the SOI layer.

7 . The structure of claim 1 , wherein the source and the drain of the first FET include a p-type dopant, and further comprising an n-type well isolated by a trench isolation adjacent each of the source and the drain of the first FET, and a deep n-type well coupling the n-type wells in the base semiconductor layer.

8 . A structure, comprising:
a trench isolation layer in a base semiconductor layer in a first region, and a semiconductor-on-insulator (SOI) substrate in a second region; a first field effect transistor (FET) in the first region adjacent to a second FET in the second region, the first FET having a source and a drain in the base semiconductor layer under the trench isolation layer and a gate electrode over the trench isolation layer over the base semiconductor layer, the second FET having a source and a drain in a semiconductor-on-insulator (SOI) layer over a buried insulator layer of the SOI substrate; and a deep trench isolation in each of the source and the drain of the first FET, the deep trench isolations integral to the trench isolation layer, the source of the first FET surrounding the deep trench isolation therein.

9 . The structure of claim 8 , wherein the gate electrode of the first FET overlaps both deep trench isolations in the source and the drain of the first FET.

10 . The structure of claim 8 , wherein the gate electrode of the first FET includes a high dielectric constant metal gate (HKMG) over the trench isolation layer.

11 . The structure of claim 8 , wherein the second FET includes a gate electrode including a high dielectric constant metal gate (HKMG) over the SOI layer.

12 . The structure of claim 8 , wherein the gate electrode of the first FET includes a gate dielectric layer including the trench isolation layer and at least one dielectric layer over the trench isolation layer.

13 . A method, comprising:
in a fully-depleted semiconductor-on-insulator (FDSOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer, forming a first field effect transistor (FET) in a first region of the FDSOI substrate by:
forming a first trench isolation and a second trench isolation spaced from the first trench isolation in the base semiconductor layer;
doping the base semiconductor layer to form a source about the first trench isolation and a drain about the second trench isolation, the source of the first FET surrounding the first trench isolation therein;
epitaxially growing a semiconductor region over the SOI layer; and
forming a gate electrode in the semiconductor region and the SOI layer using the buried insulator layer as a gate dielectric for the gate electrode.

14 . The method of claim 13 , further comprising forming a second FET in a second region of the SOI substrate adjacent to and electrically isolated from the first region by:
doping the SOI layer to form a source and a drain for the second FET therein, the source and the drain of the second FET being over the buried insulator layer; forming a gate electrode over the SOI layer between the source and the drain of the second FET.

15 . The method of claim 14 , wherein forming the gate electrode for the second FET occurs prior to forming the gate electrode for the first FET, and further comprising removing the gate electrode for the second FET from over the semiconductor region and the SOI layer in the first region prior to forming the gate electrode for the first FET.

16 . The method of claim 14 , wherein epitaxially growing the semiconductor region over the SOI layer also includes epitaxially growing a raised semiconductor region over each of the source and the drain of the second FET.

17 . The method of claim 14 , wherein doping the base semiconductor layer to form the source about the first trench isolation and the drain about the second trench isolation in the first region for the first FET also includes doping the base semiconductor layer below the buried insulator layer in the second region for the second FET.

18 . The method of claim 14 , further comprising simultaneously forming a silicide over the source, the drain, and the gate electrode of the first FET, and the source, the drain, and the gate electrode of the second FET.

19 . The method of claim 13 , wherein the source and the drain of the first FET include a p-type dopant, and wherein forming the first and second trench isolations also includes forming a third trench isolation spaced from the first trench isolation, a fourth trench isolation spaced from the third trench isolation, a fifth trench isolation spaced from the second trench isolation, and a sixth trench isolation spaced from the fifth trench isolation, and further comprising doping the base semiconductor layer with an n-type dopant to form an n-type well between the third and fourth trench isolations and between the fifth and sixth trench isolations, and doping to form a deep n-type well in the base semiconductor layer coupling the n-type wells.

20 . The method of claim 13 , wherein epitaxially growing the semiconductor region over the SOI layer also includes epitaxially growing a raised semiconductor region over each of the source and the drain of the first FET.

Assignees

• Globalfoundries Us Inc

Inventors

• Herrmann Tom
• Zhao Zhixing
• Zaka Alban
• Chen Yiching

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/84

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/7838

  Electricity · mapped topic