Ai chip

Patent metadata

Field	Value
Publication number	US-2023197711-A1
Application number	US-202117995972-A
Country	US
Kind code	A1
Filing date	Apr 14, 2021
Priority date	May 28, 2020
Publication date	Jun 22, 2023
Grant date	—

Abstract

An artificial intelligence (AI) chip includes: a plurality of memory dies each for storing data; a plurality of computing dies each of which performs a computation included in an AI process; and a system chip that controls the plurality of memory dies and the plurality of computing dies. Each of the plurality of memory dies has a first layout pattern. Each of the plurality of computing dies has a second layout pattern. A second memory die which is one of the plurality of memory dies is stacked above the first layout pattern of a first memory die which is one of the plurality of memory dies. A second computing die which is one of the plurality of computing dies is stacked above the second layout pattern of a first computing die which is one of the plurality of computing dies.

First claim

1 . An artificial intelligence (AI) chip comprising:
a plurality of memory dies each for storing data; a plurality of computing dies each of which performs a computation included in an AI process; and a system chip that controls the plurality of memory dies and the plurality of computing dies, wherein each of the plurality of memory dies has a first layout pattern, each of the plurality of computing dies has a second layout pattern, a second memory die which is one of the plurality of memory dies is stacked above the first layout pattern of a first memory die which is one of the plurality of memory dies, and a second computing die which is one of the plurality of computing dies is stacked above the second layout pattern of a first computing die which is one of the plurality of computing dies.

2 . The AI chip according to claim 1 , wherein
the system chip includes the first memory die and the first computing die.

3 . The AI chip according to claim 1 , wherein
the system chip includes an interposer, and at least one of the first memory die or the first computing die is stacked on the interposer.

4 . The AI chip according to claim 3 , wherein
the first memory die and the first computing die are stacked on the interposer.

5 . The AI chip according to claim 1 , wherein
the system chip includes a first region and a second region that do not overlap with each other in plan view, the plurality of memory dies are stacked in the first region, and the plurality of computing dies are stacked in the second region.

6 . The AI chip according to claim 1 , wherein
one of the first memory die and the first computing die is stacked above an other of the first memory die and the first computing die.

7 . The AI chip according to claim 1 , wherein
each of the plurality of computing dies includes a programmable circuit, and the programmable circuit includes an accelerator circuit for the AI process.

8 . The AI chip according to claim 7 , wherein
the programmable circuit includes a logic block and a switch block.

9 . The AI chip according to claim 1 , wherein
the computation included in the AI process includes at least one of convolution operation, matrix operation, or pooling operation.

10 . The AI chip according to claim 9 , wherein
the convolution operation includes a computation performed in a logarithmic domain.

11 . The AI chip according to claim 1 , wherein
the AI process includes error diffusion dithering.

12 . The AI chip according to claim 1 , wherein
the system chip includes:
a control block; and
a bus that electrically connects the control block to the plurality of memory dies and the plurality of computing dies.

13 . The AI chip according to claim 1 , wherein
the plurality of first layout patterns are interconnected by through conductors.

14 . The AI chip according to claim 1 , wherein
the plurality of first layout patterns are interconnected wirelessly.

15 . The AI chip according to claim 1 , wherein
the plurality of second layout patterns are interconnected by through conductors.

16 . The AI chip according to claim 1 , wherein
the plurality of second layout patterns are interconnected wirelessly.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Goto Shoichi
• Obata Koji
• Sasago Masaru
• Nakagawa Masamichi

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title