Scan test in a single-wire bus circuit

Patent metadata

Field	Value
Publication number	US-2023176120-A1
Application number	US-202117545113-A
Country	US
Kind code	A1
Filing date	Dec 8, 2021
Priority date	Dec 8, 2021
Publication date	Jun 8, 2023
Grant date	—

Abstract

A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

First claim

What is claimed is:

1 . A single-wire bus circuit comprising:
a bus pin coupled to a single-wire bus; a communication circuit coupled to the bus pin; and a driver circuit coupled to the bus pin and comprising:
a plurality of test pins coupled to the communication circuit; and
a test driver circuit configured to operate in a test mode in each of a plurality of test cycles to:
provide one or more test input values to a first subset of the plurality of test pins to thereby cause a test to be performed in the communication circuit; and
receive one or more test output values resulting from the test performed in the communication circuit via a second subset of the plurality of test pins.

2 . The single-wire bus circuit of claim 1 , wherein the driver circuit further comprises:
a switch circuit coupled between the bus pin, the communication circuit, and the test driver circuit; and a driver controller configured to:
control the switch circuit to decouple the communication circuit from the bus pin and to couple the test driver circuit to the bus pin in response to an explicit indication of the test mode; and
control the switch circuit to decouple the test driver circuit from the bus pin and to couple the communication circuit in response to an explicit indication of a communication mode.

3 . The single-wire bus circuit of claim 2 , wherein:
the driver circuit further comprises a test mode pin coupled between the driver controller and the communication circuit; and the communication circuit is configured to assert the test mode pin to provide the explicit indication of the test mode and de-assert the test mode pin to provide the explicit indication of the communication mode.

4 . The single-wire bus circuit of claim 3 , wherein the communication circuit comprises a mode detector configured to:
assert the test mode pin in response to receiving a test initiation command; and de-assert the test mode pin in response to power cycling of the single-wire bus circuit.

5 . The single-wire bus circuit of claim 4 , wherein the communication circuit comprises a receive circuit coupled to the bus pin and is configured to:
receive the test initiation command in the communication mode via the bus pin; and provide the test initiation command to the mode detector.

6 . The single-wire bus circuit of claim 1 , wherein the test driver circuit is further configured to cause a Scan test to be performed in the communication circuit in the test mode.

7 . The single-wire bus circuit of claim 6 , wherein:
the plurality of test pins comprises a Scan input (SI) pin, a Scan enable (SE) pin, a clock (CLK) pin, and a Scan output (SO) pin; the first subset of the plurality of test pins comprises the SI pin, the SE pin, and the CLK pin; the second subset of the plurality of test pins comprises the SO pin; and the test driver circuit is further configured to operate in the test mode in each of the plurality of test cycles to:
provide an SI value, an SE value, and a CLK value to the SI pin, the SE pin, and the CLK pin, respectively, to thereby cause the Scan test to be performed in the communication circuit; and
receive an SO value resulting from the Scan test performed in the communication circuit via the SO pin.

8 . The single-wire bus circuit of claim 7 , wherein each of the SI value, the SE value, and the SO value is a voltage pulse-width modulation (PWM) value.

9 . The single-wire bus circuit of claim 7 , wherein the plurality of test cycles each comprises a first bus symbol, a second bus symbol, and a third bus symbol.

10 . The single-wire bus circuit of claim 9 , wherein, in each of the plurality of test cycles, the test driver circuit is further configured to:
receive the SI value in the first bus symbol; receive the SE value in the second bus symbol; and transmit the SO value in the third bus symbol.

11 . The single-wire bus circuit of claim 10 , wherein, in each of the plurality of test cycles, the test driver circuit is further configured to derive the CLK value on the third bus symbol.

12 . The single-wire bus circuit of claim 10 , wherein in each of the plurality of test cycles, the test driver circuit is further configured to:
receive the SI value and the SE value corresponding to an immediately succeeding one of the plurality of test cycles; and transmit the SO value corresponding to an immediately preceding one of the plurality of test cycles.

13 . The single-wire bus circuit of claim 12 , wherein the driver circuit further comprises a current sink coupled to the bus pin and is configured in each of the plurality of test cycles to:
determine whether the SO value equals a binary zero or a binary one; activate the current sink in response to determining that the SO value equals the binary zero; and deactivate the current sink in response to determining that the SO value equals the binary one.

14 . The single-wire bus circuit of claim 13 , wherein the test driver circuit is further configured to activate the current sink immediately upon determining that the SO value equals the binary zero.

15 . The single-wire bus circuit of claim 7 , wherein the plurality of test cycles each comprises a first bus symbol and a second bus symbol.

16 . The single-wire bus circuit of claim 15 , wherein, in each of the plurality of test cycles, the test driver circuit is further configured to:
receive the SI value and the SE value in the first bus symbol; and transmit the SO value in the second bus symbol.

17 . The single-wire bus circuit of claim 16 , wherein, in each of the plurality of test cycles, the test driver circuit is further configured to derive the CLK value on the second bus symbol.

18 . The single-wire bus circuit of claim 16 , wherein in each of the plurality of test cycles, the test driver circuit is further configured to:
receive the SI value and the SE value corresponding to an immediately succeeding one of the plurality of test cycles; and transmit the SO value corresponding to an immediately preceding one of the plurality of test cycles.

19 . The single-wire bus circuit of claim 18 , wherein the driver circuit further comprises a current sink coupled to the bus pin and is configured in each of the plurality of test cycles to:
determine whether the SO value represents a binary zero or a binary one; activate the current sink in response to determining that the SO value equals the binary zero; and deactivate the current sink in response to determining that the SO value equals the binary one.

20 . The single-wire bus circuit of claim 17 , wherein:
the SI value and the SE value each equals a binary zero when the first bus symbol comprises a voltage pulse-width modulation (PWM) value modulated with a twenty-five percent duty cycle; the SI value equals the binary zero and the SE value equals a binary one when the first bus symbol comprises the voltage PWM value modulated with a fifty percent duty cycle; and the SI value and the SE value each equals the binary one when the first bus symbol comprises the voltage PWM value modulated with a seventy-five percent duty cycle.

Assignees

• Qorvo Us Inc

Inventors

• Hietala Alexander Wayne
• Ngo Christopher Truong
• Bunch Ryan Lee

Classifications

• G01R31/318533

  using scanning techniques, e.g. LSSD, Boundary Scan, JTAG · CPC title

• G01R31/318538 Primary

  Topological or mechanical aspects · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G01R31/318536 Primary

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title