Class d amplifier circuitry

Patent metadata

Field	Value
Publication number	US-2023170850-A1
Application number	US-202117537619-A
Country	US
Kind code	A1
Filing date	Nov 30, 2021
Priority date	Nov 30, 2021
Publication date	Jun 1, 2023
Grant date	—

Abstract

Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.

First claim

1 . Class D amplifier circuitry comprising:
input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.

2 . Class D amplifier circuitry according to claim 1 , further comprising digital signal generator circuitry configured to generate the first digital input signal.

3 . Class D amplifier circuitry according to claim 2 , further comprising digital modulator circuitry configured to generate a modulated digital signal based on a digital input signal.

4 . Class D amplifier circuitry according to claim 2 , wherein the digital signal generator circuitry is configured to selectively generate the first digital input signal according to the first modulation scheme or a second digital input signal according to the second modulation scheme.

5 . Class D amplifier circuitry according to claim 4 , further comprising:
digital modulator circuitry configured to generated a modulated digital signal based on a digital input signal; and envelope detector circuitry configured to output a signal indicative of a signal level of the digital input signal, wherein the digital signal generator circuitry is configured to generate the first digital input signal according to the first modulation scheme or the second digital input signal according to the second modulation scheme based on the signal level of the digital input signal.

6 . Class D amplifier circuitry according to claim 5 , wherein the digital signal generator is configured to generate the first digital input signal according to the first modulation scheme if the input signal level meets or exceeds a threshold, and to generate the second digital input signal according to the second modulation scheme if the input signal level is below the threshold.

7 . Class D amplifier circuitry according to claim 1 , wherein the input buffer circuitry comprises first and second reference voltage sources and a switch network operable to selectively couple the first or second reference voltage source to an output node of the input buffer circuitry based on a control signal indicative of a signal level of the first digital input signal.

8 . Class D amplifier circuitry according to claim 4 , wherein the input buffer circuitry comprises first, second and third reference voltage sources and a switch network operable to selectively couple the first, second or third reference voltage source to an output node of the input buffer circuitry based on a control signal indicative of a signal level of the second digital input signal generated.

9 . Class D amplifier circuitry according to claim 1 , wherein the first plurality N is equal to 2.

10 . Class D amplifier circuitry according to claim 1 , wherein the second plurality M is equal to 3.

11 . Class D amplifier circuitry according to claim 3 , wherein the analog input signal comprises an audio signal.

12 . Class D amplifier circuitry according to claim 1 , wherein the digital input signal, the analog modulated signal and the output signal each comprise a differential signal pair.

13 . Class D amplifier circuitry according to claim 1 , wherein the digital input signal comprises a pulse width modulated (PWM) digital signal.

14 . Class D amplifier circuitry according to claim 1 , wherein the analog modulated signal comprises a pulse width modulated (PWM) analog signal.

15 . A host device comprising Class D amplifier circuitry according to claim 1 .

16 . A host device according to claim 15 , wherein the host device comprises a laptop, notebook, netbook or tablet computer, a mobile telephone, a portable device, or an accessory device for use with a laptop, notebook, netbook or tablet computer, a mobile telephone, or a portable device.

17 . Class D amplifier circuitry comprising:
an input buffer for receiving a digital PWM input signal and outputting an analog output signal based on the digital PWM input signal; an analog modulator for generating an amplified PWM signal based on the digital PWM input signal; and an analog quantizer for generating a multi-level PWM output signal for driving a transducer based on the amplified PWM signal, wherein the multi-level output signal has a greater number of discrete signal levels than the digital PWM input signal.

18 . Class D amplifier circuitry comprising:
an input buffer for receiving a digital PWM input signal and outputting an analog output signal based on the digital PWM input signal; an analog modulator for generating an amplified PWM signal based on the digital PWM input signal; and an analog quantizer for generating a multi-level PWM output signal for driving a transducer based on the amplified PWM signal, wherein a number of discrete signal levels in the digital PWM input signal is variable based on a level of an input signal received by the Class D amplifier circuitry, and wherein the number of discrete signal levels in the digital PWM input signal is equal to or less than a number of discrete signal levels in the multi-level PWM output signal.

Assignees

• Cirrus Logic Int Semiconductor Ltd

Inventors

• Klarenbeek Johnny
• Singleton David P
• Prior Morgan T
• Wigner Jonathan T
• Dougherty Christopher M
• Cai Qi
• Bhattacharya Anindya

Classifications

• H03F3/217

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F1/0233 Primary

  by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

• H03F2200/105

  A non-specified detector of the power of a signal being used in an amplifying circuit · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title

• H03F3/181

  Low-frequency amplifiers, e.g. audio preamplifiers · CPC title