Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit

Patent metadata

Field	Value
Publication number	US-2023168958-A1
Application number	US-202217948254-A
Country	US
Kind code	A1
Filing date	Sep 20, 2022
Priority date	Nov 30, 2021
Publication date	Jun 1, 2023
Grant date	—

Abstract

An interface circuit includes a signal processing circuit configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device. The signal processing circuit includes multiple signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.

First claim

What is claimed is:

1 . An interface circuit, comprising:
a signal processing circuit, configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises: a plurality of signal processing devices; and a calibration device, coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.

2 . The interface circuit as claimed in claim 1 , wherein the interface circuit is disposed in a memory controller and the calibration procedure is triggered in response to at least one error event of the memory controller.

3 . The interface circuit as claimed in claim 1 , wherein the calibration device comprises:
an error event detection circuit, configured to detect whether at least one of a plurality of predetermined error events has occurred and generate a trigger signal when detecting that at least one of the plurality of predetermined error events has occurred; a probe circuit, configured to probe each signal processing device to generate a corresponding probe result in response to the trigger signal; and a control circuit, coupled to the error event detection circuit and the probe circuit and configured to perform the calibration procedure in response to the trigger signal and adjust the characteristic value of each signal processing device according to the corresponding probe result in the calibration procedure.

4 . The interface circuit as claimed in claim 1 , wherein the signal processing circuit is a Serializer-Deserializer.

5 . The interface circuit as claimed in claim 1 , wherein the plurality of signal processing devices comprise a regulator circuit and a frequency synthesizer circuit, and in the calibration procedure, the control circuit is configured to calibrate the regulator circuit first and then calibrate the frequency synthesizer circuit.

6 . A memory controller, coupled to a memory device and configured to control access operation of the memory device, comprising:
a host interface, configured to communicate with a host device and comprising a signal processing circuit configured to process a reception signal received from the host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises: a plurality of signal processing devices; and a calibration device, coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure, wherein in response to a trigger signal, the calibration device is configured to obtain a probe result of each signal processing device and calibrate the characteristic value of each signal processing device according to the corresponding probe result.

7 . The memory controller as claimed in claim 6 , wherein the calibration procedure is triggered in response to at least one error event of the memory controller.

8 . The memory controller as claimed in claim 6 , wherein the calibration device comprises:
an error event detection circuit, configured to detect whether at least one of a plurality of predetermined error events has occurred and generate a trigger signal when detecting that at least one of the plurality of predetermined error events has occurred; a probe circuit, configured to probe each signal processing device to generate a corresponding probe result in response to the trigger signal; and a control circuit, coupled to the error event detection circuit and the probe circuit and configured to perform the calibration procedure in response to the trigger signal and adjust the characteristic value of each signal processing device according to the corresponding probe result in the calibration procedure.

9 . The memory controller as claimed in claim 6 , wherein the signal processing circuit is a Serializer-Deserializer.

10 . The interface circuit as claimed in claim 6 , wherein the plurality of signal processing devices comprise:
a first signal processing device; and a second signal processing device, wherein the second signal processing device obtains a power signal from the first signal processing device, and in the calibration procedure, the control circuit is configured to calibrate the first signal processing device and then calibrate the second signal processing device.

11 . A method for calibrating a plurality of signal processing devices in an interface circuit, comprising:
detecting whether at least one of a plurality of predetermined error events has occurred and generating a trigger signal when detecting that at least one of the plurality of predetermined error events has occurred; probing each signal processing device in response to the trigger signal to generate a corresponding probe result; and sequentially calibrating a characteristic value of each signal processing device according to the corresponding probe result in response to the trigger signal in a calibration procedure.

12 . The method as claimed in claim 11 , wherein the interface circuit is disposed in a memory controller and the plurality of predetermined error events are error events occurred in the memory controller.

Assignees

• Silicon Motion Inc

Inventors

• Shih Fu-Jen

Classifications

• G06F11/0745 Primary

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• H04L1/0016

  involving special memory structures, e.g. look-up tables · CPC title

• G06F11/0751 Primary

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• H04L1/0061

  Error detection codes · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title