Array substrate, display panel, and display device

Patent metadata

Field	Value
Publication number	US-2023141543-A1
Application number	US-202217677763-A
Country	US
Kind code	A1
Filing date	Feb 22, 2022
Priority date	Nov 5, 2021
Publication date	May 11, 2023
Grant date	—

Abstract

An array substrate, a display panel and a display device are provided. The array substrate has a display area and a non-display area surrounding the display area. The array substrate includes: pixel circuits arranged in the display area in an array along a first direction and a second direction; a first gate driving circuit in the non-display area including first shift register units; and a second gate driving circuit in the non-display area including a plurality of second shift register units in cascade connection. The first gate driving circuit and the second gate driving circuit are electrically connected to different transistors in the pixel circuits; and an orthographic projection of the first gate driving circuit on a plane of the array substrate and an orthographic projection of the second gate driving circuit on the plane of the array substrate at least partially overlap along the second direction.

First claim

1 . An array substrate with a display area and a non-display area surrounding the display area, comprising:
a plurality of pixel circuits arranged in an array along a first direction and a second direction, wherein the plurality of pixel circuits are disposed in the display area and the first direction intersects the second direction; a first gate driving circuit in the non-display area, wherein the first gate driving circuit includes a plurality of first shift register units in cascade connection; and a second gate driving circuit in the non-display area, the second gate driving circuit and the first gate driving circuit being at a same side of the display area, wherein the second gate driving circuit includes a plurality of second shift register units in cascade connection, wherein: the first gate driving circuit and the second gate driving circuit are electrically connected to different transistors in the plurality of pixel circuits; and an orthographic projection of the first gate driving circuit on a plane of the array substrate at least partially overlaps with an orthographic projection of the second gate driving circuit on the plane of the array substrate along the second direction, and at least two of the plurality of first shift register units of the first gate driving circuit are adjacent to each other.

2 . The array substrate according to claim 1 , wherein:
the first gate driving circuit includes a scan driving circuit; and the second gate driving circuit includes a light-emitting control driving circuit.

3 . The array substrate according to claim 2 , wherein:
each pixel circuit of the plurality of pixel circuits includes first-type transistors and second-type transistors; each first shift register unit of the plurality of first shift register units includes a first-type shift register unit and a second-type shift register unit; one of the first-type shift register unit and the second-type shift register unit is electrically connected to the first-type transistors, and another one of the first-type shift register unit and the second-type shift register unit is electrically connected to the second-type transistors; the first-type transistors are N-type transistors; the second-type transistors are P-type transistors; an orthographic projection of the first-type shift register unit on the plane of the array substrate and an orthographic projection of the second-type shift register unit on the plane of the array substrate have no overlap in the second direction; and the orthographic projection of the second gate driving circuit on the plane of the array substrate and an orthographic projection of one of the first-type shift register unit and the second-type shift register unit on the plane of the array substrate overlap along the second direction.

4 . The array substrate according to claim 1 , wherein:
along the second direction, the plurality of first shift register units is distributed between at least two adjacent second shift register units of the plurality of second shift register units.

5 . The array substrate according to claim 1 , wherein:
along the second direction, the plurality of first shift register units is distributed between any two adjacent second shift register units of the plurality of second shift register units.

6 . The array substrate according to claim 5 , wherein:
the plurality of first shift register units of the first gate driving circuit includes N cascaded first shift register units; and along the second direction, i first shift register units of the N first shift register units are located between any two adjacent second shift register units, wherein i and N are positive integers and i≤N.

7 . The array substrate according to claim 6 , wherein:
i=2, and each of the plurality of second shift register units is electrically connected to two rows of the plurality of pixel circuits; or i=4, and each of the plurality of second shift register units is electrically connected to four rows of the plurality of pixel circuits.

8 . The array substrate according to claim 1 , wherein:
along the second direction, a length of each of the plurality of first shift register units is smaller than a length of each of the plurality of pixel circuits; and/or along the second direction, a length of each of the plurality of second shift register units is smaller than a length of each of the plurality of pixel circuits.

9 . The array substrate according to claim 6 , wherein:
i=2, wherein:
each second shift register unit of the plurality of second shift register units is electrically connected to two rows of the plurality of pixel circuits;
a total length of two adjacent first shift register units of the plurality of first shift register units and one corresponding second shift register unit of the plurality of second shift register units along the second direction is a first length;
a total length in the second direction of two pixel circuits of the plurality of pixel circuits adjacent along the second direction is a second length; and
the first length is same as the second length; or
i=4, wherein:

each second shift register unit of the plurality of second shift register units is electrically connected to four rows of the plurality of pixel circuits;
a total length of four adjacent first shift register units of the plurality of first shift register units and one corresponding second shift register unit of the plurality of second shift register units along the second direction is a third length;
a total length in the second direction of four pixel circuits of the plurality of pixel circuits adjacent along the second direction is a fourth length; and
the third length is same as the fourth length.

10 . The array substrate according to claim 6 , wherein:
i=2, wherein:
each second shift register unit of the plurality of second shift register units is electrically connected to two rows of the plurality of pixel circuits;
a length-width ratio of each of the plurality of first shift register units is about 4.5:1 to about 5.5:1; and
a length-width ratio of each of the plurality of second shift register units is about 4.2:1 to about 5.2:1; or
i=4, wherein:

each second shift register unit of the plurality of second shift register units is electrically connected to four rows of the plurality of pixel circuits;
a length-width ratio of each of the plurality of first shift register units is about 4.2:1 to about 5.2:1; and
a length-width ratio of each of the plurality of second shift register units is about 4.0:1 to about 5.0:1,
wherein:

the length-width ratio of one first shift register unit of the plurality of first shift register units is a ratio between a length of the first shift register unit in the first direction and a length of the first shift register unit in the second direction; and
the length-width ratio of one second shift register unit is a ratio between a length of the second shift register unit in the first direction and a length of the second shift register unit in the second direction.

11 . The array substrate according to claim 10 , wherein:
i=2, wherein:
each second shift register unit of the plurality of second shift register units is electrically connected to two rows of the plurality of pixel circuits;
a length-width ratio of each of the plurality of first shift register units is about 5.0:1; and
a length-width ratio of each of the plurality of second shift register units is about 4.7:1; or
i=4, wherein:

each second shift register unit of the plurality of second shift register units

Assignees

• Wuhan Tianma Micro Electronics Co Ltd

Inventors

• Gu Jiachang
• Peng Tao

Classifications

• G09G2310/0281

  Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title