Display Device and Driving Method for the Same

US2023136867A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023136867-A1
Application numberUS-202217895061-A
CountryUS
Kind codeA1
Filing dateAug 25, 2022
Priority dateOct 28, 2021
Publication dateMay 4, 2023
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed is a display device including: a timing controller outputting image data and a data driving control signal based on an image signal and a control signal inputted from the outside; a data driver outputting a data voltage corresponding to the image data based on the data driving control signal; and a display panel displaying an image corresponding to the data voltage, and the data driver includes: a buffer array where buffer groups, each of which is composed of one or more adjacent output buffers, are disposed; a bias current controller applying a bias current to the buffer groups; and an output circuit sequentially applying the data voltage outputted from the buffer groups to data lines in response to a source output enable signal and driving method for the same.

First claim

Opening claim text (preview).

What is claimed is: 1 . A display device comprising: a timing controller outputting image data and a data driving control signal based on an image signal and a control signal; a data driver outputting a data voltage corresponding to the image data based on the data driving control signal; and a display panel displaying an image corresponding to the data voltage, wherein the data driver comprises: a buffer array including a plurality of buffer groups, each of which is comprised of one or more adjacent output buffers; a bias current controller applying a bias current to the buffer groups; and an output circuit sequentially applying the data voltage outputted from the buffer groups to data lines, in response to a source output enable signal. 2 . The display device of claim 1 , wherein the output circuit further comprises a buffer circuit which is disposed between the buffer groups and delays the source output enable signal by a predetermined time, and sequentially delays and outputs the data voltage outputted from the buffer groups, in response to the delayed source output enable signal. 3 . The display device of claim 2 , wherein the bias current controller sequentially increases a magnitude of the bias current applied to each of the buffer groups in response to a delay time of the source output enable signal. 4 . The display device of claim 3 , wherein the buffer array comprises group parties comprised of at least one buffer group, and wherein the bias current controller controls the magnitude of the bias current differently for the group parties. 5 . The display device of claim 4 , wherein the bias current controller applies a bias current of a default value to a group party comprised of buffer groups having no delay time of the source output enable signal, and sequentially increases the magnitude of the bias current applied to the group party as the delay time of the source output enable signal increases. 6 . The display device of claim 5 , wherein the bias current is applied to at least one among both sides of the buffer groups and a center of the buffer groups. 7 . The display device of claim 5 , wherein the timing controller transmits, to the bias current controller, a first signal for indicating the number of buffer groups comprised in the group party, a second signal for indicating the default value of the bias current, and a third signal for indicating a sequential increase amount of the bias current. 8 . The display device of claim 2 , wherein the bias current is applied in a direction of at least one among both sides of the buffer groups and a center of the buffer groups, and wherein the timing controller alternates an application direction of the source output enable signal in a unit of at least one among a frame and a pixel line. 9 . The display device of claim 8 , wherein a delay time of the source output enable signal alternates in a unit of at least one among the frame and the pixel line in response to the application direction of the source output enable signal. 10 . A method of controlling the display device comprising a data driver outputting a data voltage based on a data driving control signal outputted by a timing controller, wherein the data driver comprises a buffer array including a plurality of buffer groups, each of which is comprised of one or more adjacent output buffers; and wherein the method comprises: applying a bias current to the buffer groups; applying a source output enable signal to the buffer groups by the timing controller; and sequentially applying the data voltage outputted from the buffer groups to data lines, in response to the source output enable signal. 11 . The method of claim 10 , wherein the source output enable signal is sequentially delayed and applied to the buffer groups by a buffer circuit disposed between the buffer groups. 12 . The method of claim 11 , wherein the applying the bias current to the buffer groups comprises sequentially increasing a magnitude of the bias current applied to each of the buffer groups in response to a delay time of the source output enable signal. 13 . The method of claim 12 , wherein the buffer array comprises group parties comprised of at least one buffer group, and wherein the bias current is controlled differently for the group parties. 14 . The method of claim 13 , wherein the applying the bias current to the buffer groups comprises: applying a bias current of a default value to the group party comprised of buffer groups having no delay time of the source output enable signal; and sequentially increasing and applying the magnitude of the bias current applied to the group party as the delay time of the source output enable signal increases. 15 . The method of claim 13 , further comprising: before the applying the bias current to the buffer groups, transmitting, to the data driver, a first signal for the timing controller to indicate the number of buffer groups comprised in the group party, a second signal for the timing controller to indicate the default value of the bias current, and a third signal for the timing controller to indicate a sequential increase amount of the bias current. 16 . The method of claim 10 , wherein the applying the bias current to the buffer groups comprises: applying, in a first frame, the bias current in a direction from both sides of the buffer groups to a center of the buffer groups; applying, in a second frame, the bias current in a direction from the center of the buffer groups to both sides of the buffer groups; and applying, in a third frame, the bias current in the direction from both sides of the buffer groups to the center of the buffer groups. 17 . The method of claim 10 , wherein the applying the bias current to the buffer groups comprises: applying the bias current in a direction from both sides of the buffer groups to a center of the buffer groups in response to a data voltage applied to a first pixel line; applying the bias current in a direction from the center of the buffer groups to both sides of the buffer groups in response to a data voltage applied to a second pixel line; and applying the bias current in the direction from both sides of the buffer groups to the center of the buffer groups in response to a data voltage applied to a third pixel line. 18 . A display device comprising: a timing controller outputting image data and a data driving control signal based on an image signal and a control signal; a data driver outputting a data voltage corresponding to the image data based on the data driving control signal; and a display panel displaying an image corresponding to the data voltage, wherein the data driver comprises: a buffer array including a first buffer group and a second buffer group, each of the first buffer group and the second buffer group comprised of one or more output buffers; a bias current controller applying a bias current to the buffer groups; and an output circuit including first switching elements and second switching elements applying the data voltage outputted from the buffer groups to data lines in response to a source output enable signal, the source output enable signal being applied to the first switching elements at a first timing and to the second switching elements at a second timing later than the first timing. 19 . The display device of claim 18 , wherein the bias current controller applies a first bias current to the first buffer group and a second bias current to the second buffe

Assignees

Inventors

Classifications

  • G09G3/3291Primary

    in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

  • Reduction of instantaneous peaks of current · CPC title

  • G09G3/2092Primary

    Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

  • G09G3/3275Primary

    Details of drivers for data electrodes · CPC title

  • Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

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What does patent US2023136867A1 cover?
Disclosed is a display device including: a timing controller outputting image data and a data driving control signal based on an image signal and a control signal inputted from the outside; a data driver outputting a data voltage corresponding to the image data based on the data driving control signal; and a display panel displaying an image corresponding to the data voltage, and the data drive…
Who is the assignee on this patent?
Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3291. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu May 04 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).