Algorithmic tcam based ternary lookup

Patent metadata

Field	Value
Publication number	US-2023127391-A1
Application number	US-202218088182-A
Country	US
Kind code	A1
Filing date	Dec 23, 2022
Priority date	Sep 20, 2015
Publication date	Apr 27, 2023
Grant date	—

Abstract

An algorithmic TCAM based ternary lookup method is provided. The method stores entries for ternary lookup into several sub-tables. All entries in each sub-table have a sub-table key that includes the same common portion of the entry. No two sub-tables are associated with the same sub-table key. The method stores the keys in a sub-table keys table in TCAM. Each key has a different priority. The method stores the entries for each sub-table in random access memory. Each entry in a sub-table has a different priority. The method receives a search request to perform a ternary lookup for an input data item. A ternary lookup into the ternary sub-table key table stored in TCAM is performed to retrieve a sub-table index. The method performs a ternary lookup across the entries of the sub-table associated with the retrieved index to identify the highest priority matched entry for the input data item.

First claim

What is claimed is:

1 . Integrated circuit for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable tertiary content addressable memory (TCAM) in association with the packet forwarding-related operations, the integrated circuit comprising:
other machine-readable memory for use in the packet forwarding-related operations, the machine-readable TCAM and the other machine-readable memory to store table data for use in the packet forwarding-related operations; and at least one processing unit to execute compiler-produced program instructions, the compiler-produced program instructions, when executed by the at least one processing unit resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data;
wherein:
the table data is configurable to comprise multiple tables;
at least one of the multiple tables is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
the table data is configurable to indicate packet processing rules that comprise the at least one action;
the packet processing rules are configurable to indicate one or more of:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination; and

the table indices are configurable to correspond, at least in part, to tree nodes.

2 . The integrated circuit of claim 1 , wherein:
the parallel table lookup operations involve two or more of the multiple tables.

3 . The integrated circuit of claim 2 , wherein:
an application specific integrated circuit comprises the integrated circuit.

4 . The integrated circuit of claim 3 , wherein:
the other machine-readable memory comprises programmable memory; and the at least one processing unit comprises one or more processors.

5 . The integrated circuit of claim 4 , wherein:
at least one other of the multiple tables is configurable to indicate respective mask data associated with respective entries; and the respective mask data is to be applied to certain portions of the incoming packet data.

6 . The integrated circuit of claim 5 , wherein:
another integrated circuit comprises the machine-readable TCAM.

7 . Machine-readable instructions to be executed by an integrated circuit, the integrated circuit being for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable tertiary content addressable memory (TCAM) in association with the packet forwarding-related operations, the integrated circuit comprising other machine-readable memory and at least one processing unit, the other machine-readable memory being for use in the packet forwarding-related operations, the machine-readable instructions, when executed by the integrated circuit, resulting in the integrated circuit being configured to perform certain operations comprising:
storing, in the machine-readable TCAM and the other machine-readable memory, table data for use in the packet forwarding-related operations; and executing, by the at least one processing unit, compiler-produced program instructions, the compiler-produced program instructions, when executed by the at least one processing unit resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data;
wherein:
the table data is configurable to comprise multiple tables;
at least one of the multiple tables is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
the table data is configurable to indicate packet processing rules that comprise the at least one action;
the packet processing rules are configurable to indicate one or more of:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination; and

the table indices are configurable to correspond, at least in part, to tree nodes.

8 . The machine-readable instructions of claim 7 , wherein:
the parallel table lookup operations involve two or more of the multiple tables.

9 . The machine-readable instructions of claim 8 , wherein:
an application specific integrated circuit comprises the integrated circuit.

10 . The machine-readable instructions of claim 9 , wherein:
the other machine-readable memory comprises programmable memory; and the at least one processing unit comprises one or more processors.

11 . The machine-readable instructions of claim 10 , wherein:
at least one other of the multiple tables is configurable to indicate respective mask data associated with respective entries; and the respective mask data is to be applied to certain portions of the incoming packet data.

12 . The machine-readable instructions of claim 11 , wherein:
another integrated circuit comprises the machine-readable TCAM.

13 . A method implemented using an integrated circuit, the integrated circuit being for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable tertiary content addressable memory (TCAM) in association with the packet forwarding-related operations, the integrated circuit comprising other machine-readable memory and at least one processing unit, the other machine-readable memory being for use in the packet forwarding-related operations, the method comprising:
storing, in the machine-readable TCAM and the other machine-readable memory, table data for use in the packet forwarding-related operations; and executing, by the at least one processing unit, compiler-produced program instructions, the compiler-produced program instructions, when executed by the at least one processing unit resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the o

Assignees

• Barefoot Networks Inc

Inventors

• Bosshart Patrick
• Ferrara Michael G
• Peterson Jay E S

Classifications

• H04L45/742 Primary

  Route cache; Operation thereof · CPC title

• G06F16/90339 Primary

  by using parallel associative memories or content-addressable memories · CPC title

• G11C15/04

  using semiconductor elements · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title