Semiconductor memory device and method of manufacturing the semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2023126213-A1
Application number	US-202217825873-A
Country	US
Kind code	A1
Filing date	May 26, 2022
Priority date	Oct 26, 2021
Publication date	Apr 27, 2023
Grant date	—

Abstract

The present technology includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first stack structure over a lower structure in which a cell region and a slimming region are defined, including a plurality of first gate lines, a first interlayer insulating structure over the first stack structure, a second stack structure over the first interlayer insulating structure, and a plurality of vertical plugs passing through the first stack structure, the first interlayer insulating structure and the second stack structure in the cell region.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first stack structure over a lower structure in which a cell region and a slimming region are defined, including a plurality of first gate lines; a first interlayer insulating structure over the first stack structure; a second stack structure over the first inter layer insulating structure; and a plurality of vertical plugs passing through the first stack structure, the first interlayer insulating structure and the second stack structure in the cell region.

2 . The semiconductor memory device of claim 1 , wherein an edge of the first interlayer insulating structure has a step shape in the slimming region.

3 . The semiconductor memory device of claim 1 , further comprising a second interlayer insulating structure over the first interlayer insulating structure.

4 . The semiconductor memory device of claim 3 , wherein an edge of the second interlayer insulating structure has a step shape in the slimming region.

5 . The semiconductor memory device of claim 3 , further comprising:
interlayer insulating layers formed between the first gate lines and between the second gate lines.

6 . The semiconductor memory device of claim 5 , wherein the first interlayer insulating structure and the second interlayer insulating structure are formed of a layer of the same material as the interlayer insulating layers, and
wherein an edge of the first stack structure and the second stack structure formed in the slimming region are formed in a step shape.

7 . The semiconductor memory device of claim 5 , wherein the first and the second interlayer insulating structure are thicker than each of the interlayer insulating layers.

8 . The semiconductor memory device of claim 4 , wherein a height and a distance of the step shape of the first interlayer insulating structure is different from a height and a distance of the step shape of a portion except for the first interlayer insulating structure in the first stack structure, and
a height and a distance of the step shape of the second interlayer insulating structure is different from a height and a distance of the step shape of a portion except for the second interlayer insulating structure in the second stack structure.

9 . The semiconductor memory device of claim 1 , wherein each of the vertical plugs includes a memory layer, a channel layer, and a vertical insulating layer sequentially formed along an inner wall of vertical holes vertically passing through the first stack structure and the second stack structure.

10 . The semiconductor memory device of claim 4 , wherein the first interlayer insulating structure and the second interlayer insulating structure have at least two or more step shapes.

11 . The semiconductor memory device of claim 3 , further comprising:
a third interlayer insulating structure formed between the first interlayer insulating structure and the second interlayer insulating structure.

12 . The semiconductor memory device of claim 11 , wherein the third interlayer insulating structure is thicker than each of interlayer insulating layers.

13 . The semiconductor memory device of claim 11 , wherein the vertical plugs further include a third vertical plug formed in a portion passing through the third interlayer insulating structure.

14 . The semiconductor memory device of claim 13 , wherein the third vertical plug is configured to connect a first portion and a second portion;
wherein the first portion is passing through the first stack structure and the first interlayer insulating structure; and wherein the second portion is passing through the second stack structure and the second interlayer insulating structure to each other among channel layers included in the vertical plugs.

15 . The semiconductor memory device of claim 1 , wherein each of the vertical plugs comprises:
a vertical hole vertically passing through the first stack structure and the second stack structure; a memory layer formed along an inner wall of the vertical hole; a channel layer formed along an inner wall of the memory layer; a vertical insulating layer formed in a region surrounded by the channel layer; and a vertical channel separation structure vertically separating the vertical insulating layer, the channel layer, and the memory layer in a vertical direction.

16 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a first stack structure on a lower structure in which a cell region and a slimming region are defined; forming a first interlayer insulating structure over the first stack structure; forming a second interlayer insulating structure over the first interlayer insulating structure; forming a second stack structure on the second interlayer insulating structure; forming a vertical plug passing through the second stack structure, the second interlayer insulating structure, the first interlayer insulating structure and the first stack structure in the cell region; and performing an etching process so that an edge of the second stack structure, the second interlayer insulating structure, the first stack structure, and the first interlayer insulating structure has a step shape, a height and a distance of the step shape of the first interlayer insulating structure is different from a height and a distance of the step shape of a portion except for the first interlayer insulating structure, and a height and a distance of the step shape of the second interlayer insulating structure is different from a height and a distance of the step shape of a portion except for the second interlayer insulating structure, in the slimming region.

17 . The method of claim 16 , wherein in the first stack structure, interlayer insulating layers and sacrificial layers are alternately stacked on the lower structure, and then the first interlayer insulating structure is formed, and the first interlayer insulating structure is formed of the same material as the interlayer insulating layers.

18 . The method of claim 16 , wherein the second interlayer insulating structure is formed of the same material as the first interlayer insulating structure.

19 . The method of claim 16 , wherein the etching process is performed by sequentially using mask patterns having an opening exposing the second stack structure and the first stack structure formed in the slimming region and decreasing to a constant length.

20 . The method of claim 19 , wherein etching process is performed so that the second stack structure or the first stack structure exposed by the opening is removed to the same depth each time the mask patterns are changed.

21 . The method of claim 20 , wherein an interlayer insulating layer and a sacrificial layer formed in each of the first stack structure or the second stack structure are removed to substantially the same depth, during the etching process.

22 . The method of claim 21 , wherein the first interlayer insulating structure or the second interlayer insulating structure is removed to a depth substantially equal to the depth to which the interlayer insulating layer and the sacrificial layer are removed from the first stack structure or the second stack structure, during the etching process.

23 . The method of claim 16 ,
wherein forming the vertical plug comprises:
forming a vertical hole passing through the second stack structure and the first stack structure; and
sequentially forming a

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Geun
• Kim Jang Won
• Jang Jung Shik

Classifications

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/30 Primary

  characterised by the memory core region · CPC title

• H10B12/31 Primary

  having a storage electrode stacked over the transistor · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title