Nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-2023126012-A1
Application number	US-202217866904-A
Country	US
Kind code	A1
Filing date	Jul 18, 2022
Priority date	Oct 22, 2021
Publication date	Apr 27, 2023
Grant date	—

Abstract

Provided is a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.

First claim

1 . A nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells; an address decoder configured to decode a row address and a column address from an address signal; a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array according to the decoded row address; a second voltage generator configured to generate a bit line operating voltage of the memory cell array according to the decoded column address; a page buffer circuit configured to activate according to the bit line operating voltage and to store data to be stored in or read from at least one memory cell; and a temperature unit configured to determine, from a temperature range table storing a plurality of selection signals mapped to each of a plurality of temperatures ranges, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of at least one of the first or second voltage generator based on a selection signal mapped to the determined temperature range.

2 . The nonvolatile memory device of claim 1 , wherein the temperature unit includes:
a digital temperature sensor configured to measure a temperature state of the nonvolatile memory device in real time and to output the measured temperature state as the temperature code; a coefficient selector configured to output a coefficient, of a plurality of coefficients respectively corresponding to the plurality of selections signals, based on the selection signal mapped to the determined temperature range; and an intercept selector configured to output an intercept, of a plurality of intercepts respectively corresponding to the plurality of selection signals, based on the selection signal mapped to the determined temperature range.

3 . The nonvolatile memory device of claim 2 , wherein the temperature unit further includes:
a multiplier configured to multiply the temperature code by the output coefficient; an adder configured to add the selected intercept to an output from the multiplier; a multiplexer configured to output an output of the adder when the digital temperature sensor is activated; a comparator configured to output a current compensation level by comparing a previous compensation level with a current reference voltage to which a resistance value corresponding to an output signal of the adder is applied; and a temperature compensation transistor configured to be gated according to the current compensation level and to generate the adjusted power supply voltage.

4 . The nonvolatile memory device of claim 1 , wherein the page buffer circuit includes:
a precharge circuit comprising at least one transistor controlled by a bit line setup signal output from a control circuit; and a shutoff circuit comprising at least one transistor controlled by a bit line shutoff signal, wherein the second voltage generator includes a bit line shutoff signal generator configured to adjust a voltage level of the bit line shutoff signal according to an output of the temperature unit.

5 . The nonvolatile memory device of claim 4 , wherein the bit line shutoff signal generator is configured to adjust the voltage level of the bit line shutoff signal according to a current compensation level determined based on the selection signal mapped to the determined temperature range.

6 . The nonvolatile memory device of claim 1 , wherein
the address decoder is configured to select at least one of a plurality of word lines according to the row address decoded from the address signal and to apply the world line operating voltage to each of the selected word line, and the first voltage generator is configured to adjust a voltage level of the word line operating voltage according to a current compensation level according to the selection signal mapped to the determined temperature range.

7 . The nonvolatile memory device of claim 2 , wherein the plurality of coefficients and the plurality of intercepts include:
a plurality of bit line coefficients respectively associated with a bit line operation for each of the plurality of temperature ranges; a plurality of bit line intercepts respectively associated with the bit line operation for each of the plurality of temperature ranges; a plurality of word line coefficients respectively associated with a word line operation for each of the plurality of temperature ranges; and a plurality of word line intercepts respectively associated with the word line operation for each of the plurality of temperature ranges.

8 . A nonvolatile memory device comprising:
a cell region comprising the memory cell array comprising the plurality of memory cells on a first substrate; and a peripheral circuit region on a second substrate including a plurality of circuit elements and a temperature unit, the plurality of circuit elements configured to access the memory cell array and the temperature unit configured to sense a real-time temperature of the memory cell array and to determine a temperature range, from among a plurality of temperature ranges, for the sensed real-time temperature and to adjust an operating voltage to be applied to the memory cell array based on a compensation value mapped to the determined temperature range.

9 . The nonvolatile memory device of claim 8 , wherein the plurality of circuit devices include:
an address decoder configured to decode a row address and a column address from an address signal; a first voltage generator configured to generate a word line operating voltage for the memory cell array according to the decoded row address; a second voltage generator configured to generate a bit line operating voltage according to the decoded column address; and a page buffer circuit configured to activate according to the bit line operating voltage and to store data to be stored in or read from at least one memory cell.

10 . The nonvolatile memory device of claim 9 , wherein the page buffer circuit includes:
a precharge circuit comprising at least one transistor controlled by a bit line setup signal output from a control circuit; and a shutoff circuit including at least one transistor controlled by a bit line shutoff signal, wherein the second voltage generator is configured to adjust a voltage level of the bit line shutoff signal by adjusting a power supply voltage according to the compensation value.

11 . The nonvolatile memory device of claim 9 , wherein
the address decoder is configured to select at least one of a plurality of word lines according to the decoded row address and to apply the word line operating voltage to the selected word line, and the first voltage generator is configured to adjust a voltage level of the word line operating voltage by adjusting a power supply voltage according to the compensation value.

12 . (canceled)

13 . The nonvolatile memory device of claim 12 , wherein the temperature unit further includes:
a coefficient selector configured to output a coefficient, of a plurality of coefficients respectively corresponding to the plurality of selections signals, based on the selection signal mapped to the determined temperature range; and an intercept selector and configured to output an intercept, of a plurality of intercepts respectively corresponding to the plurality of selections signals, based on the selection signal mapped to the determined temperature range.

14 . The nonvolatile memory device of claim 13 , wherein the plurality of coefficients include, respectively, a plurality of bit line coefficients and a plurality of word line coeffici

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Bong-Kil
• Nam Sang-Wan
• Baek Jong Min
• Jeon Min Ki
• Jung Woo Chul
• Choi Yoon-Hee

Classifications

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title