Power amplifiers

Patent metadata

Field	Value
Publication number	US-2023125874-A1
Application number	US-202217695500-A
Country	US
Kind code	A1
Filing date	Mar 15, 2022
Priority date	Oct 22, 2021
Publication date	Apr 27, 2023
Grant date	—

Abstract

A power amplifier structure includes at least one power amplifier circuit. The power amplifier circuit includes a transistor of a first type connected in series with a transistor of a second type connected between the same voltage supply. In a non-limiting nonexclusive example, an n-type transistor is connected in series with a p-type transistor connected between Vdd. The power amplifier structure can include two amplifier circuits configured in a differential amplifier structure. The differential amplifier structure includes two amplifier circuits operably connected in parallel between the same voltage supply.

First claim

What is claimed is:

1 . A power amplifier structure, comprising:
a first transistor of a first type configurated as a transconductance amplifier, the first transistor operably connected to a first power supply; a second transistor of a second type configurated as a current buffer amplifier, the second transistor operably connected to the first transistor at an intermediate node; a first inductor operably connected between the first power supply and a connecting node, the second transistor operably connected to the connecting node; and a second inductor operably connected between the intermediate node and a second power supply, wherein the first transistor, the second transistor, and the first inductor are connected in series between the first power supply.

2 . The power amplifier structure of claim 1 , further comprising:
a resistor operably connected between a terminal of the first transistor and a third power supply; and a capacitor operably connected to a terminal of the second transistor.

3 . The power amplifier structure of claim 2 , further comprising a fourth power supply operably connected to the terminal of the second transistor.

4 . The power amplifier structure of claim 1 , wherein:
the first transistor of the first type is an n-type transistor; the second transistor of the second type is a p-type transistor; the first power supply is Vss; and the second power supply is Vdd.

5 . The power amplifier structure of claim 1 , wherein:
the first transistor of the first type is a p-type transistor; the second transistor of the second type is an n-type transistor; the first power supply is Vdd; and the second power supply is Vss.

6 . The power amplifier structure of claim 1 , wherein the first and the second transistors are each implemented as a metal-oxide-silicon transistor.

7 . The power amplifier structure of claim 1 , further comprising an output signal line operably connected to the connecting node.

8 . The power amplifier structure of claim 1 , wherein at least one of the first inductor or the second inductor is implemented as co-planar waveguide transmission line.

9 . The power amplifier structure of claim 1 , wherein the first inductor functions as a primary coil of a transformer.

10 . The power amplifier structure of claim 9 , further comprising a neutralization capacitor operably connected to the intermediate node of the power amplifier circuit.

11 . The power amplifier structure of claim 10 , wherein:
the transformer is a first transformer; and the power amplifier structure further comprises a second transformer operably connected to a gate of the second transistor of the second type.

12 . An electronic device, comprising:
an antenna; and a power amplifier structure operably connected to the antenna, the power amplifier structure comprising:
a first terminal of a first inductor operably connected to a first power supply and a second terminal of the first inductor operably connected to a connecting node;
a first terminal of a first transistor of a first type operably connected to the connecting node and a second terminal of the first transistor of the first type operably connected to an intermediate node;
a first terminal of a second transistor of a second type operably connected to the intermediate node and a second terminal of the second transistor of the second type operably connected to the first power supply;
an output signal line operably connected to the connecting node;
a first terminal of a second inductor operably connected to the intermediate node and a second terminal of the second inductor operably connected to a second power supply;
a capacitor operably connected to a third terminal of the first transistor of the first type; and a resistor operably connected to a third terminal of the second transistor of the second type, wherein the first transistor of the first type, the second transistor of the second type, and the first inductor are connected in series between the first power supply.

13 . The device of claim 12 , wherein:
the first transistor of the first type is an n-type transistor; the second transistor of the second type is a p-type transistor; the first power supply is Vdd; and the second power supply is Vss.

14 . The device of claim 13 , wherein the capacitor is operably connected between the third terminal of the first transistor of the first type and the second power supply.

15 . The device of claim 12 , wherein:
the first transistor of the first type is a p-type transistor; the second transistor of the second type is an n-type transistor; the first power supply is Vss; and the second power supply is Vdd.

16 . The device of claim 15 , wherein the capacitor is operably connected between the third terminal of the first transistor of the first type and the first power supply.

17 . The device of claim 12 , wherein the first transistor of the first type is configured as a common-gate amplifier and the second transistor of the second type is configured as a common-source amplifier.

18 . The device of claim 12 , further comprising a neutralization capacitor operably connected to the intermediate node of the power amplifier circuit.

19 . A method, comprising:
receiving an input signal at a gate terminal of a first transistor, the first transistor being a first type; receiving a reference signal at a gate terminal of a second transistor, the second transistor being a second type complementary to the first type; receiving a first power supply signal at a first terminal of the first transistor; receiving the first power supply signal at a first terminal of a first inductor, the first inductor having a second terminal connected to a second terminal of the first transistor at a connecting node; receiving a second power supply signal at a first terminal of a second inductor, the second inductor having a second terminal connected to an intermediate node where a second terminal of the first transistor is connected to a second terminal of the second transistor; and providing an output signal at the intermediate node, where the output signal is greater than the input signal.

20 . The method of claim 19 , wherein the first transistor is configured as a transconductance amplifier to output a current at the second terminal of the first transistor that is proportional to the input signal, and wherein the second transistor is configured as a current buffer amplifier to absorb the current output by the first transistor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wen-Sheng
• Yeh En-Hsiang
• Yeh Tzu-Jin

Classifications

• H03F3/45188

  Non-folded cascode stages · CPC title

• H03F1/565

  using inductive elements · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H04B1/18

  Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title

• H03F2200/534

  Transformer coupled at the input of an amplifier · CPC title